FN7503.2 November 12, 2010 functions on the chip are referenced to ITR and have
參數(shù)資料
型號: EL4583AIS-T7
廠商: Intersil
文件頁數(shù): 10/10頁
文件大?。?/td> 0K
描述: IC SYNC SEPARATOR S-H 50% 16SOIC
標準包裝: 1,000
類型: 同步分離器
應(yīng)用: 多媒體顯示器,測試設(shè)備
安裝類型: 表面貼裝
封裝/外殼: 16-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 16-SOIC
包裝: 帶卷 (TR)
9
FN7503.2
November 12, 2010
functions on the chip are referenced to ITR and have
excellent supply voltage rejection.
To improve noise immunity, the output of the 3 pole filter is
brought out to pin 7. It is recommended to AC couple the
output to pin 8, the video input pin. In case of strong clean
video signal, the video input pin, pin 8, can be driven by the
signal directly.
Comparator C2 on the input to the sample and hold block
(S/H) compares the leading and trailing edges of the sync
pulse with a threshold voltage VR2 which is referenced at a
fixed level above the clamp voltage VR1. The output of C2
initiates the timing one-shots for gating the sample and hold
circuits. The sample of the sync tip is delayed by 0.8s to
enable the actual sample of 2s to be taken on the optimum
section of the sync pulse tip. The acquisition time of the
circuit is about three horizontal lines. The double poly CMOS
technology enables long time constants to be achieved with
small high quality on-chip capacitors. The back porch
voltage is similarly derived from the trailing edge of sync,
which also serves to cut off the tip sample if the gate time
exceeds the tip period. Note that the sample and hold gating
times will track RSET through IOT.
The 50% level of the sync tip is derived through the resistor
divider R1 and R2, from the sample and held voltages VTIP
and VBP and applied to the plus input of comparator C1.
This comparator has built in hysteresis to avoid false
triggering. The output of C2 is a digital 5V signal which feeds
the C/S output buffer B1, the vertical, back porch and
odd/even functions.
The vertical circuit senses C/S edges and initiates an
integrator which is reset by the shorter horizontal sync
pulses but times out with the longer vertical sync pulse
widths. The internal timing circuits are referenced to IOT and
VR3, the timeout period being inversely proportional to the
timing current. The vertical output pulse is started on the first
serration pulse in the vertical interval and is then self-timed
out. In the absence of a serration pulse, an internal timer will
default the start of vertical.
The Horizontal circuit senses C/S edges and produces the
true horizontal pulses of nominal width 5s. The leading
edge is triggered from the leading edge of the input H sync,
with the same prop. delay as composite sync. The half line
pulses present in the input signal during vertical blanking are
removed with an internal 2H eliminator circuit. The 2H
eliminator initiates a time out period after a horizontal pulse
is generated. The time out period is a function of IOT which
is set by RSET.
The back porch is triggered from the sync tip trailing edge
and initiates a one-shot pulse. The period of this pulse is
again a function of IOT and will therefore track the scan rate
set by RESET.
The odd/even circuit (O/E) tracks the relationship of the
horizontal pulses to the leading edge of the vertical output
and will switch on every field at the start of vertical. Pin 13 is
high during an odd field.
Loss of video signal can be detected by monitoring the No
Signal Detect Output pin 10. The VTIP voltage held by the
sample and hold is compared with a voltage level set by RLV
on pin 2. Pin 10 output goes high when the VTIP falls below
RLV set value.
VTIP voltage is also passed through an amplifier with gain of
2 and buffed to pin 9. This provides an indication of signal
strength. This signal (Level Output) can be used for AGC
applications.
EL4583A
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