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| 型號： | EK22 |
| 廠商： | Apex Microtechnology Corporation |
| 英文描述： | EVALUATION KIT FOR PA94/PA95 |
| 中文描述： | 評估板PA94/PA95 |
| 文件頁數(shù)： | 1/5頁 |
| 文件大小： | 503K |
| 代理商： | EK22 |
APEX MICROTECHNOLOGY CORPORATION TELEPHONE (520) 690-8600 FAX (520) 888-3329 ORDERS (520) 690-8601 EMAIL prodlit@apexmicrotech.com
1
INTRODUCTION
The EK22 evaluation kit is designed to provide a convenient
way to breadboard design ideas for the SA56 PWM amplifiers.
The EVAL25 evaluation board is pre-wired for all required
and recommended external components. The EVAL25 also
includes a breadboard area for constructing your application
circuit including provisions for an output filter. Please refer to
applications note 32 in the Apex catalog for guidance in filter
component selection. The 1μF ceramic capacitors supplied
with the kit are for high frequency bypassing of the VS and
VDD supplies (C1 – C3 on the EVAL25 board). An additional
user supplied low ESR capacitor of at least 10uF per amp
of output current is required for adequate bypass of the VS
supply (C4 on the EVAL25 board). Please refer to applica-
tions note 30 for help with power supply bypassing and other
useful information.
SA56 PROTOTYPE BETA SAMPLES
This evaluation kit is supplied for evaluation of SA56 pro-
totype beta samples. There are some limitations to the SA56
prototypes that must be noted. Suggestions to minimize the
effect of these limitations are included.
The SA56 combines both high speed high power switching
and low level analog signals on a single silicon chip. The dif-
ficulty in achieving clean noise free operation is much greater
then that of discrete or hybrid microcircuit designs. Though
much care and attention has been given to these considerations
in the design and layout of the SA56, there is still some work
to be done and these prototypes do not switch as cleanly as
necessary for completely trouble free operation.
Grounding for the SA56 is critical. The EVAL25 board has
separate ground paths for signal ground (SGND) and power
ground (PGND). The signal and power grounds are common
at one point on the SA56. Ground loops can be formed if these
two grounds are tied together externally. These two grounds
are not tied together on the EVAL25 board through trace rout-
ing. When building your evaluation circuit, insure that each
component referenced to ground is tied to the proper ground
path. External components at the high speed, high current
output of the SA56 must be returned to PGND.
Analog Mode Operation of the SA56 prototype is affected
by switching noise through non-linear operation towards the
PWM duty cycle extremes. This limits the useable duty cycle
range of the SA56 prototype. The use of external flyback
diodes and the use of RC snubbers from each output to
ground reduces switching noise, increasing the usable duty
cycle range. However the duty cycle should be limited within
the range of 5% to 95%.
This kit is supplied with four schottky diodes, p/n SB5100,
for use as external flyback diodes (D1 – D4). It is recom-
mended that diodes D1 – D4 be used regardless of the mode
of operation.
In addition four 20 ohm, 5W resistors, and two 15nF, 100V
capacitors are supplied for use as an RC snubber for each
output (C9, R3a, R3b and C10, R4a, R4b). The snubbers are
especially useful in reducing the noise generated by the high
dv/dt during output switching. The power dissipated in the
snubber components can be estimated by;
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P = V
2
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Where:
P is the power dissipated
V is the VS supply voltage
C is the snubber capacitor value (15nF)
FSW is the switching frequency.
It also is recommended that a low pass RC filter be included
on the PWM_IN line for analog mode operation (R2 and C8).
A 100 ohm resistor and 2.7nF capacitor worked well for R2
and C8 value during design verification testing. However these
may not be the best choice for switching frequency and load
configurations other then that used during design verification
testing. It is up to the user to determine the best values to use
for a given application.
Start-up Faults of the SA56 protection circuits due to noise
generated by high current transient pulses at start-up may
occur. The SA56 has an internal start-up reset pulse to handle
these transients, but the duration of these transients is often
longer then the reset pulse.
These transient current pulses will trip the short circuit and
over current protection if a high current output is commanded
at start-up. It is best if the SA56 can be started up with low
output current demand. Examples are starting with the PWM
input at mid-range in analog mode, or starting with reduced
VS supply voltage.
If a “soft start” is not practical, a start-up reset pulse can be
generated on the EVAL25 board with a few external compo-
nents. Figure 1 is an example of this reset pulse generator.
When VDD is applied, the disable pin will be pulled high by
capacitor C11 until C11 is discharged by R1. This generates
a reset pulse on the disable pin. After the reset pulse is dis-
charged, R1 holds disable at logic low for normal operation. The
time constant of C11 and R1 must be a couple of milliseconds
longer then the rise time of the VDD supply. A good choice
for R1 is 10K - 20K ohms. The VS supply must be turned on
before the VDD supply.
Figure 1. Start-up Reset
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