參數(shù)資料
型號: EDS6416CHTA
廠商: Elpida Memory, Inc.
英文描述: 64M bits SDRAM (4M words x 16 bits)
中文描述: 6400位的SDRAM(4分字× 16位)
文件頁數(shù): 1/49頁
文件大?。?/td> 716K
代理商: EDS6416CHTA
Document No. E0442E40 (Ver. 4.0)
Date Published June 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2004-2005
DATA SHEET
64M bits SDRAM
EDS6416AHBH, EDS6416CHBH
(4M words
×
16 bits)
Description
The EDS6416AHBH, EDS6416CHBH are 64M bits
SDRAMs organized as 1,048,576 words
×
16 bits
×
4
banks. All inputs and outputs are synchronized with
the positive edge of the clock.
Supply voltages are 3.3V (EDS6416AHBH) and 2.5V
(EDS6416CHBH).
It is packaged in 60-ball FBGA.
Features
3.3V and 2.5V power supply
Clock frequency: 166MHz/133MHz (max.)
Single pulsed /RAS
×
16 organization
4 banks can operate simultaneously and
independently
Burst read/write operation and burst read/single
write operation capability
2 variations of burst sequence
Sequential (BL = 1, 2, 4, 8, full page)
Interleave (BL = 1, 2, 4, 8)
Programmable /CAS latency (CL): 2, 3
Byte control by UDQM and LDQM
Refresh cycles: 4096 refresh cycles/64ms
2 variations of refresh
Auto refresh
Self refresh
FBGA package with lead free solder (Sn-Ag-Cu)
RoHS compliant
Pin Configurations
/xxx indicate active low signal.
VSS
1
A
B
C
D
E
F
G
H
J
K
L
M
N
2
3
4
5
6
7
DQ14
DQ13
DQ12
DQ10
DQ9
DQ8
NC
NC
DQ15
VSSQ
VDDQ
DQ11
VSSQ
VDDQ
NC
VSS
UDQM
DQ0
VDDQ
VSSQ
DQ4
VDDQ
VSSQ
NC
VDD
LDQM
VDD
DQ1
DQ2
DQ3
DQ5
DQ6
DQ7
NC
/WE
NC
CKE
A11
A8
CLK
NC
A9
A7
/RAS
NC
BA1
A0
/CAS
/CS
BA0
A10
P
R
A6
VSS
A5
A4
A2
A3
A1
VDD
(Top view)
60-ball FBGA
A0 to A11
BA0, BA1
DQ0 to DQ15
/CS
/RAS
/CAS
/WE
LDQM, UDQM
Address input
Bank select address
Data-input/output
Chip select
Row address strobe
Column address strobe
Write enable
Input/output mask
CKE
CLK
VDD
VSS
VDDQ
VSSQ
NC
Clock enable
Clock input
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
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