參數(shù)資料
型號: EDI8F8513C
英文描述: 512Kx8 Static RAM CMOS, Module(512Kx8 CMOS靜態(tài)RAM模塊)
中文描述: 512Kx8靜態(tài)RAM的CMOS模塊(512Kx8的CMOS靜態(tài)內存模塊)
文件頁數(shù): 1/6頁
文件大?。?/td> 76K
代理商: EDI8F8513C
EDI8F8513C
512Kx8 Static Ram
1
EDI8F8513C Rev. 0 4/98 ECO#9500
Pin Configurations and Block Diagram
Features
512Kx8 bit CMOS Static
Random Access Memory
Access Times 20 thru 35ns
TTL Compatible Inputs and Outputs
Fully Static, No Clocks
High Density Packaging
32 Pin DIP, JEDEC Pinout, No. 415
Single +5V (±10%) Supply Operation
Pin Names
A-A18
Address Inputs
E
Chip Enable
W
Write Enable
G
Output Enable
DQ-DQ7
Common Data Input/Output
VCC
Power (+5V±10%)
VSS
Ground
NC
No Connection
512Kx8 Static RAM
CMOS, Module
The EDI8F8513C is a 4096K bit CMOS Static RAM based
on four 128Kx8 or Static RAMs mounted on a multi-layered
epoxy laminate (FR4) substrate.
Functional equivalence to the monolithic four megabit Static
RAM is achieved by utilization of an on-board decoder that
interprets the higher order address(es) to select one of
the128Kx8 RAMs.
The 32 pin DIP pinout adheres to the JEDEC standard for
the four megabit device, to ensure compatibility with future
monolithics.
All inputs and outputs are TTL compatible and operate from
a single 5V supply. Fully asynchronous, the EDI8F8513C
requires no clocks or refreshing for operation.
Electronic Designs Incorporated
One Research Drive Westborough, MA 01581 USA 508-366-5151 FAX 508-836-4850
http://www.electronic-desings.com
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A
DQ
DQ1
DQ2
VSS
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VCC
A15
A17
W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
A-A16
W
G
A17-A18
E
DECODER
DQ-DQ7
128Kx8
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