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參數(shù)資料
| 型號： | EDI488MEV6SI |
| 廠商： | ELECTRONIC DESIGNS INC |
| 元件分類： | DRAM |
| 英文描述： | 8M X 8 EDO DRAM, 60 ns, PDSO32 |
| 封裝： | PLASTIC, TSOP2-32 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 442K |
| 代理商： | EDI488MEV6SI |
4
White Electronic Designs Corporation Phoenix, AZ (602) 437-1520
EDI488MEV-RP
AC CHARACTERISTICS (1)
(VCC = 3.0V
±10%, VIH/VIL = 2.0/0.8V, VOH/VOL = 2.0/0.8V, TA = 0°C to +70°C)
Symbol
60ns
70ns
Parameter
Min
Max
Min
Max
Units
Data set-up time (8)
tDS
00
ns
Data hold time (8)
tDH
10
15
ns
Refresh period (4K, 8K Normal)
tREF
64
ms
Write Command set-up time (6)
tWCS
00
ns
CAS to WE delay time (6)
tCWD
32
39
ns
RAS to WE delay time (6)
tRWD
77
89
ns
Column address to WE delay time (6)
tAWD
47
54
ns
CAS precharge to WE delay time
tCPWD
54
64
ns
CAS set-up time CAS-before-RAS refresh
tCSR
10
ns
CAS hold time (CAS-before-RAS refresh)
tCHR
10
15
ns
RAS to CAS precharge time
tRPC
55
ns
CAS precharge time (CBR counter test cycle)
tCPT
20
30
ns
Access time from CAS precharge (3)
tCPA
35
40
ns
Hyper page cycle time
tHPC
25
30
ns
Hyper page read-modify-write cycle time
tHPRWC
56
71
ns
CAS precharge time (Hyper page cycle)
tCP
10
ns
RAS pulse width (Hyper page cycle)
tRASP
60
200K
70
200K
ns
RAS hold time from CAS precharge
tRHCP
35
40
ns
OE access time
tOEA
15
20
ns
OE to data delay
tOED
13
15
ns
CAS precharge to WE delay time
tCPWD
54
64
ns
Output buffer turn off delay from OE
tOEZ
0130
15
ns
OE command hold time
tOEH
15
20
ns
WE to RAS precharge time (C-B-R refresh)
tWRP
10
ns
WE to RAS hold time (C-B-R refresh)
tWRH
10
ns
Output data hold time
tDOH
55
ns
Output buffer turn off delay from RAS
tREZ
3153
20
ns
Output buffer turn off delay from WE
tWEZ
3153
20
ns
WE to data delay
tWED
15
20
ns
OE to CAS hold time
tOCH
55
ns
CAS hold time to OE
tCHO
55
ns
OE precharge time
tOEP
55
ns
WE pulse width (Hyper Page Mode)
tWPE
55
ns
RAS pulse width (C-B-R self refresh)
tRASS
100
ns
RAS precharge time (C-B-R self refresh)
tRPS
110
ns
CAS hold time (C-B-R self refresh)
tCHS
-50
ns
NOTES:
1. An initial pause of 200
s is required after power-up followed by any 8 ROR or CBR cycles before proper device operation is achieved.
2. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between VIH (min) and VIL (max) and
are assumed to be 5ns for all inputs.
3. Measured with a load of equivalent to 2 TTL (5V device) loads and 100pF.
4. Operation within the tRCD(max) limit insures that tRAC (max) can be met. tRCD (max) is specified as a reference point only. If tRCD is greater than the
specified tRCD (max) limit, then access time is controlled exclusively by tCAC.
5. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to VOH or VOL.
6. tWCS, tRWD, tCWD, tAWD and tCPWD are non restrictive operating parameters. They are included in the data sheet as electric characteristics only. If tWCS
≥
tWCS (min), the cycle is an early write cycle and the data output will remain high impedance for the duration of the cycle. If tCWD
≥ tCWD (min), tRWD ≥
tRWD (min), tAWD
≥ tAWD (min) and tCPWD ≥ tCPWD (min), then the cycle is a read-modify-write cycle and the data output will contain the data read from
the selected address. If neither of the above conditions is satisfied, the condition of the data out is indeterminate.
7. Either tRCH or tRRH must be satisfied for a read cycle.
8. These parameters are referenced to the CAS falling edge in early write cycles and to the WE falling edge in read-modify-write cycles.
9. Operation within the tRAD (max) limit insures that tRAC (max) can be met. tRAD (max) is specified as a reference point only. If tRAD is greater than the
specified tRAD (max) limit, then access time is controlled by tAA.
10. Assumes that tCRD
≥ tCRD (max).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EDI488MEV6SM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 EDO Page Mode DRAM |
| EDI488MEV7SI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 EDO Page Mode DRAM |
| EDI488MEV7SM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 EDO Page Mode DRAM |
| EDI4F3232F6M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x32 Fast Page Mode DRAM Module |
| EDI4F3232F7M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x32 Fast Page Mode DRAM Module |
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