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參數(shù)資料
| 型號： | EDI2KG46464V95D |
| 英文描述： | 4x64Kx64, 3.3V Synchronous Flow-Through Card Module(4x64Kx64, 3.3V，9.5ns,同步靜態(tài)RAM卡模塊(流通結(jié)構(gòu)）) |
| 中文描述： | 4x64Kx64，3.3V的同步流動，通過卡模塊（4x64Kx64，3.3伏，9.5ns，同步靜態(tài)內(nèi)存卡模塊（流通結(jié)構(gòu)）） |
| 文件頁數(shù)： | 4/8頁 |
| 文件大?。?/td> | 126K |
| 代理商： | EDI2KG46464V95D |
EDI2KG46464V
2 Megabyte Synchronous
Card Edge DIMM
4
EDI2KG46464V Rev. 0 4/98 ECO#9976
*Stress greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions greater than those indicated
in operational sections of this specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
Absolute Maximum Ratings*
Voltage on Vcc Relative to Vss
-0.5V to +4.6V
Vin
-0.5V to Vcc +0.5V
Storage Temperature
-55°C to +125°C
Operating Temperature (Commercial)
0°C to +70°C
Operating Temperature (Industrial)
-40°C to +85°C
Short Circuit Output Current
10 mA
Synchronous Only - Truth Table
Operation
E1\
E2\
E3\
E4\
GW\
G\
ZZ
CLK
DQ
Synchronous Write-Bank 1
L
H
L
H
L
High-Z
Synchronous Read-Bank 1
L
H
L
Synchronous Write-Bank 2
H
L
H
L
H
L
High-Z
Synchronous Read-Bank 2
H
L
H
L
Synchronous Write-Bank 3
H
L
H
L
H
L
High-Z
Synchronous Read-Bank 3
H
L
H
L
Synchronous Write-Bank 4
H
L
H
L
High-Z
Synchronous Read-Bank 4
H
L
H
L
Snooze Mode
X
H
X
High-Z
Pin Descriptions
DIMM Pins
Symbol
Type
Description
3, 5, 7, 9, 13, 15,
A0-A15
Input
Addresses: These inputs are registered and must meet the setup and hold
17, 19, 23, 20, 18,
Synchronous
times around the rising edge of CLK. The burst counter generates internal
16, 14, 10, 8, 6
addresses associated with A0 and A1, during burst and wait cycle.
38
GW\
Input
Global Write: This active LOW input allows a full 72-bit WRITE to occur
Synchronous
independent of the BWE\ and BWx\ lines and must meet the setup and hold
times around the rising edge of CLK.
27
CLK
Input
Clock: This signal registers the addresses, data, chip enables, write control
Synchronous
and burst control inputs on its rising edge. All synchronous inputs must
meet setup and hold times around the clock’s rising edge.
36, 32,
E1\, E2\
Input
Bank Enables: These active LOW inputs are used to enable each individual
35, 31
E3\, E4\
Synchronous
bank and to gate ADSP\.
37
G\
Input
Output Enable: This active LOW asynchronous input enables the data output drivers.
ZZ
Input
Snooze: These active HIGH inputs put the individual banks in low power
Asynchronous
consumption standby mode. For normal operation, this input has to be either
LOW or NC (no connect).
Various
DQ0-63
Input/Output
Data Inputs/Outputs: First byte is DQ0-7, second byte is DQ8-15, third byte is
DQ16-23, fourth byte is DQ24-31, fifth byte is DQ32-39, sixth byte is
DQ40-47, seventh byte is DQ48-55 and the eight byte is DQ56-64.
Various
Vcc
Supply
Core power supply: +3.3V -5%/+10%
Various
Vss
Ground
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