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參數資料
| 型號： | EDI3DG328V8D1 |
| 英文描述： | 8Megx32 Synchronous High Density DRAM Modules 3.3V(125MHz,3.3V,8M x32同步高密度動態(tài)RAM模塊) |
| 中文描述： | 8Megx32同步高密度DRAM模塊3.3（125MHz的，3.3，8分X32號，同步高密度動態(tài)內存模塊） |
| 文件頁數： | 1/3頁 |
| 文件大?。?/td> | 97K |
| 代理商： | EDI3DG328V8D1 |
EDI3DG328V
1
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
8Mx32 Synchronous DRAM SO-DIMM, 3.3V
FEATURES
s Cycle time of 10ns, 12ns and 15ns
s Packaging:
144 pin SO-DIMM (Package 396)
s Burst Mode Operation (Sequential & Interleave)
s Auto & Self Refresh Capability (4096 cycles /64ms)
s LVTTL compatible inputs and outputs
s MRS cycle with address key programs
s Burst Length (1, 2, 4, 8 & Full Page)
s Data Scramble
s All inputs are sampled at the positive edge of the system clock
s Serial Presence Detect with EEPROM
s Single 3.3 Volts Operation
The EDI3DG328V are organized as 8Megx32 Synchronous high
density DRAM Modules which are based on 4 CMOS 8Megx8bit
DRAMs with 2 or 4 banks in a TSOP package which are mounted
on an FR4 substrate. The module also includes a serial EEPROM
in an 8-pin TSOP package.
The module is a 144 Pin Small Outline Dual In-Line Memory
module with gold contacts.
PIN DESCRIPTION
PIN CONFIGURATION
A0-12
Address lines
BA0-1
Bank Select
DQ0-15,
Data Input/Output
DQ32-47
CLK-CKL1
Clock Input
RAS\
Row Address Strobe
CAS\
Column Address Strobe
CKE0
Clock Enable Input
DQM0,1,4,5
DQM
CS0\
Chip Select Input
WE\
Write Enable
SDA
Serial Data I/O
SCL
Serial Clock
VCC
Power Supply
VSS
Ground
NC
No Connection
NOTE:
DQMs vs Data I/Os
DQM0 controls DQ0-7
DQM1 controls DQ8-15
DQM4 controls DQ32-39
DQM5 controls DQ40-47
NOTES:
1. A12 (Pin 70) is NC when using 4 bank devices
2. BA1 (Pin 110) is on C when using 2 bank devices
Pin Symbol
Pin Symbol Pin Symbol Pin Symbol
1VSS
2VSS
73
NC
74
CLK1
3DQ0
4DQ32
75
VSS
76
VSS
5DQ1
6DQ33
77
NC
78
NC
7DQ2
8DQ34
79
NC
80
NC
9DQ3
10
DQ35
81
VCC
82
VCC
11
VCC
12
VCC
83
NC
84
NC
13
DQ4
14
DQ36
85
NC
86
NC
15
DQ5
16
DQ37
87
NC
88
NC
17
DQ6
18
DQ38
89
NC
90
NC
19
DQ7
20
DQ39
91
VSS
92
VSS
21
VSS
22
VSS
93
NC
94
NC
23
DQM0
24
DQM4
95
NC
96
NC
25
DQM1
26
DQM5
97
NC
98
NC
27
VCC
28
VCC
99
NC
100
NC
29
A0
30
A3
101
VCC
102
VCC
31
A1
32
A4
103
A6
104
A7
33
A2
34
A5
105
A8
106
A9
35
VSS
36
VSS
107
VSS
108
VSS
37
DQ8
38
DQ40
109
A9
110
BA1
39
DQ9
40
DQ41
111 A10/AP
112
A11
41
DQ10
42
DQ42
113
VSS
114
VCC
43
DQ11
44
DQ43
115
NC
116
NC
45
VCC
46
VCC
117
NC
118
NC
47
DQ12
48
DQ44
119
VSS
120
VSS
49
DQ13
50
DQ45
121
NC
122
NC
51
DQ14
52
DQ46
123
NC
124
NC
53
DQ13
54
DQ45
125
NC
126
NC
55
DQ14
56
DQ46
127
NC
128
NC
57
NC
58
NC
129
VCC
130
VCC
59
NC
60
NC
131
NC
132
NC
61
CLK0
62
CKE0
133
NC
134
NC
63
VCC
64
VCC
135
NC
136
NC
65
RAS\
66
CAS\
137
NC
138
NC
67
WE\
68
NC
139
VSS
140
VSS
69
CS0\70
A12/NC
141
SDA
142
SCL
71
NC
72
NC
143
VCC
144
VCC
January 1998 Rev. 0
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