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參數(shù)資料
| 型號： | EDI2KG46464V10D |
| 英文描述： | 4x64Kx64, 3.3V Synchronous Flow-Through Card Module(4x64Kx64, 3.3V，10ns,同步靜態(tài)RAM卡模塊(流通結(jié)構(gòu)）) |
| 中文描述： | 4x64Kx64，3.3V的同步流動，通過卡模塊（4x64Kx64，3.3伏，10納秒，同步靜態(tài)內(nèi)存卡模塊（流通結(jié)構(gòu)）） |
| 文件頁數(shù)： | 1/8頁 |
| 文件大?。?/td> | 126K |
| 代理商： | EDI2KG46464V10D |
EDI2KG46464V
2 Megabyte Synchronous
Card Edge DIMM
1
EDI2KG46464V Rev. 0 4/98 ECO#9976
The EDI2KG46464VxxD is a Synchronous SRAM, 60
position Dual Key; Card Edge DIMM (120 contacts)
Module, organized as 4x64Kx64. The Module contains
eight (8) Synchronous Burst Ram Devices, packaged in
the industry standard JEDEC 14mmx20mm TQFP placed
on a Multilayer FR4 Substrate. The module architecture
is defined as a Synchronous Only, Flow-Through, Early
Write device. This Module provides high performance,
ultra fast access times at a cost per bit benefit over BiC
MOS Asynchronous devices. As well as improved cost
per bit, the use of Synchronous or Synchronous burst
devices or modules can ease the memory subsystem
design by reducing or easing the memory controller
requirement.
Synchronous operations are in relation to an externally
supplied clock, registered address, registered global
write, registered enables as well as an Asynchronous
Output enable. All Read and Write operations are
performed in Quad Words (64 bit operations).
Write cycles are internally self timed and are initiated by
a rising clock edge. This feature relieves the designer
the task of developing external pulse width circuitry.
4x64Kx64 Synchronous
Flow-Through Architecture
Clock Controlled Registered Bank Enables (E1\,
E2\, E3, E4\)
Clock Controlled Registered Address
Clock Controlled Registered Global Write (GW\)
Aysnchronous Output Enable (G\)
Internally self-timed Write
Module Sleep Mode (ZZ)
Gold Lead Finish
3.3V +10% Operation
Access Speed(s): TKHQV=9.5, 10, 11,12, 15ns
Common Data I/O
High Capacitance (30pf) drive, at rated Access
Speed
Single total array Clock
Multiple Vcc and Gnd
Advanced
Module Features
DQ0-DQ63
Input/Output Bus
A0-A15
Address Bus
E1\, E2\, E3\, E4\
Synchronous Bank Enables
Clk
Array Clock
GW\
Synchronous Global Write Enable
G\
Asynchronous Output Enable
ZZ
Module Sleep Enable
Vcc
3.3V Power Supply
Vss
Gnd
Pin Names
Electronic Designs Incorporated
One Research Drive Westborough, MA 01581USA 508-366-5151 FAX 508-836-4850
Electronic Designs Europe Ltd. Shelley House, The Avenue Lightwater, Surrey GU18 5RF
United Kingdom 01276 472637 FAX: 01276 473748
http://www.electronic-designs.com
ADVANCED
4x64Kx64, 3.3V
Synchronous Flow-Through
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PDF描述 |
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| EDI2KG46464V11D | 4x64Kx64, 3.3V Synchronous Flow-Through Card Module(4x64Kx64, 3.3V，11ns,同步靜態(tài)RAM卡模塊(流通結(jié)構(gòu)）) |
| EDI2KG46464V15D | 4x64Kx64, 3.3V Synchronous Flow-Through Card Module(4x64Kx64, 3.3V，15ns,同步靜態(tài)RAM卡模塊(流通結(jié)構(gòu)）) |
| EDI2KG46464V95D | 4x64Kx64, 3.3V Synchronous Flow-Through Card Module(4x64Kx64, 3.3V，9.5ns,同步靜態(tài)RAM卡模塊(流通結(jié)構(gòu)）) |
| EDI3DG328V10D1 | 8Megx32 Synchronous High Density DRAM Modules 3.3V(100MHz,3.3V,8M x32同步高密度動態(tài)RAM模塊) |
| EDI3DG328V8D1 | 8Megx32 Synchronous High Density DRAM Modules 3.3V(125MHz,3.3V,8M x32同步高密度動態(tài)RAM模塊) |
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