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參數(shù)資料
| 型號(hào)： | EDI2KG464128V10D |
| 英文描述： | 4x128Kx64, 3.3V Synchronous Flow-Through Card Module(4x128Kx64, 3.3V，10ns,同步靜態(tài)RAM卡模塊(流通結(jié)構(gòu)）) |
| 中文描述： | 4x128Kx64，3.3V的同步流動(dòng)，通過卡模塊（4x128Kx64，3.3伏，10納秒，同步靜態(tài)內(nèi)存卡模塊（流通結(jié)構(gòu)）） |
| 文件頁數(shù)： | 1/7頁 |
| 文件大?。?/td> | 109K |
| 代理商： | EDI2KG464128V10D |
EDI2KG464128V
4 Megabyte Synchronous
Card Edge DIMM
1
EDI2KG464128V Rev. 0 3/98 ECO#9977
The EDI2KG64128VxxD is a Synchronous SRAM, 60
position Card Edge DIMM (120 contacts) Module, orga-
nized as 4x128Kx64. The Module contains eight (8)
Synchronous Burst Ram Devices, packaged in the in-
dustry standard JEDEC 14mmx20mm TQFP placed on
a Multilayer FR4 Substrate. The module architecture is
defined as a Synchronous Only, Flow-Through, Early
Write Device. This module provides High Performance,
Ultra Fast access times at a cost per bit benefit over
BiCMOS Asynchronous SRAM based devices. As well
as improved cost per bit, the use of Synchronous or
Synchronous Burst devices or modules can ease the
memory subsystem design by reducing or easing the
memory controller requirement.
Synchronous operations are in relation to an externally
supplied clock, Registered Address, Registered Global
Write, Registered Enables as well as an Asynchronous
Output enable. All read and write operations to this
module are performed on Quad Words (64 bit opera-
tions).
Write cycles are internally self timed and are initiated by
a rising clock edge. This feature relieves the designer
the task of developing external write pulse width circuitry.
4x128Kx64 Synchronous
Flow-Through Architecture
Clock Controlled Registered Bank Enables (E1\,
E2\, E3, E4\)
Clock Controlled Registered Address
Clock Controlled Registered Global Write (GW\)
Aysnchronous Output Enable (G\)
Internally self-timed Write
Module Sleep Mode enable (ZZ)
Gold Lead Finish
3.3V +10% Operation
Access Speed(s): TKHQV=9.5, 10, 11, 12, 15ns
Common Data I/O
High Capacitance (30pf) drive, at rated Access
Speed
Single total array Clock
Multiple Vcc and Gnd
Advanced
Module Features
DQ0-DQ63
Input/Output Bus
A0-A15
Address Bus
E1\, E2\, E3\, E4\
Synchronous Bank Enables
Clk
Array Clock
GW\
Synchronous Global write Enable
G\
Asynchronous Output Enable
ZZ
Module Sleep Enable
Vcc
3.3V Power Supply
Vss
Gnd
Pin Names
Electronic Designs Incorporated
One Research Drive Westborough, MA 01581USA 508-366-5151 FAX 508-836-4850
http://www.electronic-designs.com
4x128Kx64, 3.3V
Synchronous Flow-Through
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EDI2KG464128V11D | 4x128Kx64, 3.3V Synchronous Flow-Through Card Module(4x128Kx64, 3.3V，11ns,同步靜態(tài)RAM卡模塊(流通結(jié)構(gòu)）) |
| EDI2KG464128V12D | 4x128Kx64, 3.3V Synchronous Flow-Through Card Module(4x128Kx64, 3.3V，12ns,同步靜態(tài)RAM卡模塊(流通結(jié)構(gòu)）) |
| EDI2KG464128V15D | 4x128Kx64, 3.3V Synchronous Flow-Through Card Module(4x128Kx64, 3.3V，15ns,同步靜態(tài)RAM卡模塊(流通結(jié)構(gòu)）) |
| EDI2KG464128V95D | 4x128Kx64, 3.3V Synchronous Flow-Through Card Module(4x128Kx64, 3.3V，9.5ns,同步靜態(tài)RAM卡模塊(流通結(jié)構(gòu)）) |
| EDI2KG46464V10D | 4x64Kx64, 3.3V Synchronous Flow-Through Card Module(4x64Kx64, 3.3V，10ns,同步靜態(tài)RAM卡模塊(流通結(jié)構(gòu)）) |
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