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參數(shù)資料
| 型號： | EDI2GG46464V10D |
| 英文描述： | 4x64Kx64, 3.3V Synchronous Flow-Through SRAM Card Module(4x64Kx64, 3.3V，10ns,同步靜態(tài)RAM卡模塊(流通結(jié)構(gòu)）) |
| 中文描述： | 4x64Kx64，3.3V的同步流通過的SRAM卡模塊（4x64Kx64，3.3伏，10納秒，同步靜態(tài)內(nèi)存卡模塊（流通結(jié)構(gòu)）） |
| 文件頁數(shù)： | 3/8頁 |
| 文件大小： | 244K |
| 代理商： | EDI2GG46464V10D |
3
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
EDI2GG46464V
G\
GW\
E1\
GW\
G\
E\
DQ
64Kx32
GW\
G\
E\
DQ
64Kx32
GW\
G\
E\
DQ
64Kx32
GW\
G\
E\
DQ
64Kx32
E3\
GW\
G\
E\
DQ
64Kx32
GW\
G\
E\
DQ
64Kx32
GW\
G\
E\
DQ
64Kx32
GW\
G\
E\
DQ
64Kx32
E2\
E4\
DQ0-DQ31
DQ32-DQ63
CLK
A0-A15
FUNCTIONAL BLOCK DIAGRAM
DQ0-63
Input/Output Bus
A0-15
Address Bus
E1\, E2\,
Synchronous Bank
E3\, E4\
Enables
CLK
Array Clock
GW\
Synchronous Global
Write Enable
G\
Asynchronous Output Enable
Vcc
3.3V Power Supply
Vss
Ground
NC
No Connect
PIN NAMES
PIN DESCRIPTIONS
DIMM Pins
Symbol
Type
Description
3, 5, 7, 9, 13, 15,
A0-15
Input
Addresses: These inputs are registered and must meet the setup and hold times around the rising edge of CLK.
17, 19, 23, 20, 18,
Synchronous
The burst counter generates internal addresses associated with A0 and A1, during burst and wait cycle.
16, 14, 10, 8, 6
38
GW\
Input
Global Write: This active LOW input allows a full 72-bit WRITE to occur independent of the BWE\ and BWx\ lines
Synchronous
and must meet the setup and hold times around the rising edge of CLK.
27
CLK
Input
Clock: This signal registers the addresses, data, chip enables, write control and burst control inputs on its rising
Synchronous
edge. All synchronous inputs must meet setup and hold times around the clock’s rising edge.
36, 32,
E1\, E2\
Input
Bank Enables: These active LOW inputs are used to enable each individual bank and to gate ADSP\.
35, 31
E3\, E4\
Synchronous
37
G\
Input
Output Enable: This active LOW asynchronous input enables the data output drivers.
Various
DQ0-63
Input/Output
Data Inputs/Outputs: First byte is DQ0-7, second byte is DQ8-15, third byte is DQ16-23, fourth byte is DQ24-31,
fifth byte is DQ32-39, sixth byte is DQ40-47, seventh byte is DQ48-55 and the eight byte is DQ56-64.
Various
Vcc
Supply
Core power supply: +3.3V -5%/+10%
Various
Vss
Ground
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PDF描述 |
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| EDI2GG46464V11D | 4x64Kx64, 3.3V Synchronous Flow-Through SRAM Card Module(4x64Kx64, 3.3V，11ns,同步靜態(tài)RAM卡模塊(流通結(jié)構(gòu)）) |
| EDI2GG46464V15D | 4x64Kx64, 3.3V Synchronous Flow-Through SRAM Card Module(4x64Kx64, 3.3V，15ns,同步靜態(tài)RAM卡模塊(流通結(jié)構(gòu)）) |
| EDI2GG46464V95D | 4x64Kx64, 3.3V Synchronous Flow-Through SRAM Card Module(4x64Kx64, 3.3V，9.5ns,同步靜態(tài)RAM卡模塊(流通結(jié)構(gòu)）) |
| EDI2KG464128V10D | 4x128Kx64, 3.3V Synchronous Flow-Through Card Module(4x128Kx64, 3.3V，10ns,同步靜態(tài)RAM卡模塊(流通結(jié)構(gòu)）) |
| EDI2KG464128V11D | 4x128Kx64, 3.3V Synchronous Flow-Through Card Module(4x128Kx64, 3.3V，11ns,同步靜態(tài)RAM卡模塊(流通結(jié)構(gòu)）) |
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