參數(shù)資料
型號(hào)： EDD5116ADTA-5C
廠商： ELPIDA MEMORY INC
元件分類(lèi)： DRAM
英文描述： REC3-SR_DR/H1 Series - Econoline Regulated DC-DC Converters; Input Voltage (Vdc): 12V; Output Voltage (Vdc): 15V; Power: 3W; Low Cost 3W converter in DIP24 Package; 1kVDC Isolation; Regulated Output; UL Approved; Continuous Short Circuit Protection; Internal SMD design; 3 Pinout Options, 3 Case Styles.; Efficiency to 75%
中文描述： 32M X 16 DDR DRAM, 0.7 ns, PDSO66
封裝： PLASTIC, TSOP2-66
文件頁(yè)數(shù)： 5/48頁(yè)
文件大?。?/td> 555K
代理商： EDD5116ADTA-5C
EDD5108ADTA-5C, EDD5116ADTA-5C
Preliminary Data Sheet E539E10 (Ver. 1.0)
5
DC Characteristics 1 (TA = 0 to +70
°
C, VDD, VDDQ = 2.6V ± 0.1V, VSS, VSSQ = 0V)
max.
Parameter
Symbol
Grade
×
8
×
16
Unit
Test condition
Notes
Operating current (ACT-
PRE)
Operating current
(ACT-READ-PRE)
Idle power down standby
current
IDD0
160
160
mA
CKE
≥
VIH,
tRC = tRC (min.)
CKE
≥
VIH, BL = 4,CL = 3,
tRC = tRC (min.)
1, 2, 9
IDD1
210
220
mA
1, 2, 5
IDD2P
3
3
mA
CKE
≤
VIL
4
Floating idle standby current IDD2F
35
35
mA
CKE
≥
VIH, /CS
≥
VIH
DQ, DQS, DM = VREF
CKE
≥
VIH, /CS
≥
VIH
DQ, DQS, DM = VREF
4, 5
Quiet idle standby current
IDD2Q
20
20
mA
4, 10
Active power down standby
current
IDD3P
30
30
mA
CKE
≤
VIL
3
Active standby current
IDD3N
70
70
mA
CKE
≥
VIH, /CS
≥
VIH
tRAS = tRAS (max.)
3, 5, 6
Operating current
(Burst read operation)
Operating current
(Burst write operation)
IDD4R
290
310
mA
CKE
≥
VIH, BL = 2, CL = 3 1, 2, 5, 6
IDD4W
290
310
mA
CKE
≥
VIH, BL = 2,CL = 3 1, 2, 5, 6
Auto Refresh current
IDD5
330
330
mA
tRFC = tRFC (min.),
Input
≤
VIL or
≥
VIH
Input
≥
VDD – 0.2 V
Input
≤
0.2 V
Self refresh current
IDD6
4
4
mA
Operating current
(4 banks interleaving)
Notes: 1. These IDD data are measured under condition that DQ pins are not connected.
2. One bank operation.
3. One bank active.
4. All banks idle.
5. Command/Address transition once per one clock cycle.
6. DQ, DM and DQS transition twice per one clock cycle.
7. 4 banks active. Only one bank is running at tRC = tRC (min.)
8. The IDD data on this table are measured with regard to tCK = tCK (min.) in general.
9. Command/Address transition once every two clock cycle.
10. Command/Address stable at
≥
VIH or
≤
VIL.
IDD7A
530
550
mA
BL = 4
1, 5, 6, 7
DC Characteristics 2 (TA = 0 to +70
°
C, VDD, VDDQ = 2.6V ± 0.1V, VSS, VSSQ = 0V)
Parameter
Symbol
min.
max.
Unit
Test condition
Notes
Input leakage current
ILI
–2
2
μA
VDD
≥
VIN
≥
VSS
Output leakage current
ILO
–5
5
μA
VDDQ
≥
VOUT
≥
VSS
Output high current
IOH
–15.2
—
mA
VOUT = 1.95V
Output low current
IOL
15.2
—
mA
VOUT = 0.35V
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