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參數(shù)資料
| 型號： | EDD5116ADTA-5C |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類： | DRAM |
| 英文描述： | REC3-SR_DR/H1 Series - Econoline Regulated DC-DC Converters; Input Voltage (Vdc): 12V; Output Voltage (Vdc): 15V; Power: 3W; Low Cost 3W converter in DIP24 Package; 1kVDC Isolation; Regulated Output; UL Approved; Continuous Short Circuit Protection; Internal SMD design; 3 Pinout Options, 3 Case Styles.; Efficiency to 75% |
| 中文描述： | 32M X 16 DDR DRAM, 0.7 ns, PDSO66 |
| 封裝： | PLASTIC, TSOP2-66 |
| 文件頁數(shù)： | 15/48頁 |
| 文件大小： | 555K |
| 代理商： | EDD5116ADTA-5C |
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EDD5108ADTA-5C, EDD5116ADTA-5C
Preliminary Data Sheet E539E10 (Ver. 1.0)
15
Function Truth Table
The following tables show the operations that are performed when each command is issued in each state of
the DDR SDRAM.
Current state
/CS
/RAS /CAS /WE
Address
Command
Operation
Next state
Precharging*
1
H
×
×
×
×
DESL
NOP
ldle
L
H
H
H
×
NOP
NOP
ldle
L
H
H
L
×
BST
ILLEGAL*
11
—
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL*
11
—
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL*
11
—
L
L
H
H
BA, RA
ACT
ILLEGAL*
11
—
L
L
H
L
BA, A10
PRE, PALL
NOP
ldle
L
L
L
×
×
ILLEGAL
—
Idle*
2
H
×
×
×
×
DESL
NOP
ldle
L
H
H
H
×
NOP
NOP
ldle
L
H
H
L
×
BST
ILLEGAL*
11
—
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL*
11
—
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL*
11
—
L
L
H
H
BA, RA
ACT
Activating
Active
L
L
H
L
BA, A10
PRE, PALL
NOP
Refresh/
Self refresh*
12
Mode register set*
12
ldle
ldle/
Self refresh
ldle
L
L
L
H
×
REF, SELF
Refresh
(auto-refresh)*
3
L
L
L
L
MODE
MRS
H
×
×
×
×
DESL
NOP
ldle
L
H
H
H
×
NOP
NOP
ldle
L
H
H
L
×
BST
ILLEGAL
—
L
H
L
×
×
ILLEGAL
—
L
L
×
×
×
ILLEGAL
—
Activating*
4
H
×
×
×
×
DESL
NOP
Active
L
H
H
H
×
NOP
NOP
Active
L
H
H
L
×
BST
ILLEGAL*
11
—
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL*
11
—
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL*
11
—
L
L
H
H
BA, RA
ACT
ILLEGAL*
11
—
L
L
H
L
BA, A10
PRE, PALL
ILLEGAL*
11
—
L
L
L
×
×
ILLEGAL
—
Active*
5
H
×
×
×
×
DESL
NOP
Active
L
H
H
H
×
NOP
NOP
Active
L
H
H
L
×
BST
ILLEGAL
Active
L
H
L
H
BA, CA, A10
READ/READA
Starting read operation Read/READA
L
H
L
L
BA, CA, A10
WRIT/WRITA
Starting write operation
Write
recovering/
precharging
—
L
L
H
H
BA, RA
ACT
ILLEGAL*
11
L
L
H
L
BA, A10
PRE, PALL
Pre-charge
Idle
L
L
L
×
×
ILLEGAL
—
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EDD5108AFTA-5 | 512M bits DDR SDRAM |
| EDD5108ADTA-6BL-E | 512M bits DDR SDRAM |
| EDD5108ADTA-7BL-E | 512M bits DDR SDRAM |
| EDD5108AFTA-7A-E | 512M bits DDR SDRAM |
| EDD5108AFTA-7B-E | 512M bits DDR SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EDD5116ADTA-5CLI-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR SDRAM WTR (Wide Temperature Range) |
| EDD5116ADTA-6B | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR SDRAM |
| EDD5116ADTA-6B-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR SDRAM |
| EDD5116ADTA-6BL | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR SDRAM |
| EDD5116ADTA-6BL-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR SDRAM |
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