參數(shù)資料
型號(hào)： EBE51UD8AEFA-6E-E
廠商： ELPIDA MEMORY INC
元件分類： DRAM
英文描述： Circular Connector; No. of Contacts:26; Series:MS27466; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:17; Circular Contact Gender:Socket; Circular Shell Style:Wall Mount Receptacle RoHS Compliant: No
中文描述： 64M X 64 DDR DRAM MODULE, 0.45 ns, DMA240
封裝： ROHS COMPLIANT, DIMM-240
文件頁(yè)數(shù)： 18/22頁(yè)
文件大小： 223K
代理商： EBE51UD8AEFA-6E-E
EBE51UD8AEFA
Data Sheet E0584E30 (Ver. 3.0)
18
Pin Functions
CK, /CK (input pin)
The CK and the /CK are the master clock inputs. All inputs except DMs, DQSs and DQs are referred to the cross
point of the CK rising edge and the VREF level. When a read operation, DQSs and DQs are referred to the cross
point of the CK and the /CK. When a write operation, DMs and DQs are referred to the cross point of the DQS and
the VREF level. DQSs for write operation are referred to the cross point of the CK and the /CK.
/CS (input pin)
When /CS is low, commands and data can be input. When /CS is high, all inputs are ignored. However, internal
operations (bank active, burst operations, etc.) are held.
/RAS, /CAS, and /WE (input pins)
These pins define operating commands (read, write, etc.) depending on the combinations of their voltage levels.
See "Command operation".
A0 to A13 (input pins)
Row address (AX0 to AX13) is determined by the A0 to the A13 level at the cross point of the CK rising edge and the
VREF level in a bank active command cycle. Column address (AY0 to AY9) is loaded via the A0 to the A9 at the
cross point of the CK rising edge and the VREF level in a read or a write command cycle. This column address
becomes the starting address of a burst operation.
A10 (AP) (input pin)
A10 defines the precharge mode when a precharge command, a read command or a write command is issued. If
A10 = high when a precharge command is issued, all banks are precharged. If A10 = low when a precharge
command is issued, only the bank that is selected by BA1, BA0 is precharged. If A10 = high when read or write
command, auto-precharge function is enabled. While A10 = low, auto-precharge function is disabled.
BA0 and BA1 (input pins)
BA0, BA1 are bank select signals (BA). The memory array is divided into bank 0, bank 1, bank 2 and bank 3. (See
Bank Select Signal Table)
[Bank Select Signal Table]
BA0
BA1
Bank 0
L
L
Bank 1
H
L
Bank 2
L
H
Bank 3
H
H
Remark: H: VIH. L: VIL.
CKE (input pin)
CKE controls power down and self-refresh. The power down and the self-refresh commands are entered when the
CKE is driven low and exited when it resumes to high.
The CKE level must be kept for 1 CK cycle at least, that is, if CKE changes at the cross point of the CK rising edge
and the VREF level with proper setup time tIS, at the next CK rising edge CKE level must be kept with proper hold
time tIH.
DQ (input and output pins)
Data are input to and output from these pins.
DQS and /DQS (input and output pin)
DQS and /DQS provide the read data strobes (as output) and the write data strobes (as input).
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PDF描述
EBE51UD8AGFA-4A-E 512MB Unbuffered DDR2 SDRAM DIMM (64M words x 64 bits, 1 Rank)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EBE51UD8AGFA 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512MB Unbuffered DDR2 SDRAM DIMM (64M words x 64 bits, 1 Rank)
EBE51UD8AGFA-4A-E 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512MB Unbuffered DDR2 SDRAM DIMM (64M words x 64 bits, 1 Rank)
EBE51UD8AGFA-5C-E 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512MB Unbuffered DDR2 SDRAM DIMM (64M words x 64 bits, 1 Rank)
EBE51UD8AGFA-6E-E 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512MB Unbuffered DDR2 SDRAM DIMM (64M words x 64 bits, 1 Rank)
EBE51UD8AGWA 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512MB Unbuffered DDR2 SDRAM DIMM
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