參數(shù)資料
型號(hào)： EBE51ED8AEFA-4A-E
廠(chǎng)商： ELPIDA MEMORY INC
元件分類(lèi)： DRAM
英文描述： LJT 5C 5#16 SKT RECP
中文描述： 64M X 72 DDR DRAM MODULE, 0.6 ns, DMA240
封裝： ROHS COMPLIANT, DIMM-240
文件頁(yè)數(shù)： 17/22頁(yè)
文件大?。?/td> 186K
代理商： EBE51ED8AEFA-4A-E
EBE51ED8AEFA
Data Sheet E0585E20 (Ver. 2.0)
17
ODT AC Electrical Characteristics (DDR2 SDRAM Component Specification)
Parameter
Symbol
min.
max.
Unit
Notes
ODT turn-on delay
tAOND
2
2
tCK
ODT turn-on
tAON
tAC(min)
tAC(max)
+
1000
ps
1
ODT turn-on (power down mode)
tAONPD
tAC(min)
+
2000
2tCK
+
tAC(max)
+
1000
ps
ODT turn-off delay
tAOFD
2.5
2.5
tCK
ODT turn-off
tAOF
tAC(min)
tAC(max)
+
600
ps
2
ODT turn-off (power down mode)
tAOFPD
tAC(min)
+
2000
2.5tCK
+
tAC(max)
+
1000
ps
ODT to power down entry latency
tANPD
3
3
tCK
ODT power down exit latency
tAXPD
8
8
tCK
Notes: 1. ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on.
ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND.
2. ODT turn off time min is when the device starts to turn off ODT resistance.
ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD.
AC Input Test Conditions
Parameter
Symbol
Value
Unit
Notes
Input reference voltage
VREF
0.5
×
VDDQ
V
1
Input signal maximum peak to peak swing
VSWING(max.)
1.0
V
1
Input signal maximum slew rate
SLEW
1.0
V/ns
2, 3
Notes: 1. Input waveform timing is referenced to the input signal crossing through the VREF level applied to the
device under test.
2. The input signal minimum slew rate is to be maintained over the range from VIL(DC) (max.) to VIH(AC)
(min.) for rising edges and the range from VIH(DC) (min.) to VIL(AC) (max.) for falling edges as shown in
the below figure.
3. AC timings are referenced with input waveforms switching from VIL(AC) to VIH(AC) on the positive
transitions and VIH(AC) to VIL(AC) on the negative transitions.
VSWING(max.)
TR
TF
VIH (DC)(min.)
VIL (AC)(max.)
TF
AC Input Test Signal Wave forms
Start of falling edge input timing
Start of rising edge input timing
Falling slew =
VDDQ
VIH (AC)(min.)
VIH (DC)(min.)
VIL (DC)(max.)
VIL (AC)(max.)
VSS
VREF
VIH (AC) min.
VIL (DC)(max.)
TR
Rising slew =
VTT
Measurement point
DQ
RT =25
Output Load
相關(guān)PDF資料
PDF描述
EBE51ED8AGFA LJT 24C 12#16 12#12 SKT PLUG
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EBE51ED8ABFA-4A-E 512MB Unbuffered DDR2 SDRAM DIMM (64M words x 72 bits, 1 Rank)
EBE51RD8AEFA 512MB Registered DDR2 SDRAM DIMM (64M words x 72 bits, 1 Rank)
EBE51RD8AEFA-4A-E Circular Connector; No. of Contacts:5; Series:MS27466; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:15; Circular Contact Gender:Socket; Circular Shell Style:Wall Mount Receptacle RoHS Compliant: No
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EBE51ED8AEFA-5C-E 制造商:ELPIDA 制造商全稱(chēng):Elpida Memory 功能描述:512MB Unbuffered DDR2 SDRAM DIMM (64M words x 72 bits, 1 Rank)
EBE51ED8AEFA-6 制造商:ELPIDA 制造商全稱(chēng):Elpida Memory 功能描述:512MB Unbuffered DDR2 SDRAM DIMM (64M words x 72 bits, 1 Rank)
EBE51ED8AEFA-6E-E 制造商:ELPIDA 制造商全稱(chēng):Elpida Memory 功能描述:512MB Unbuffered DDR2 SDRAM DIMM (64M words x 72 bits, 1 Rank)
EBE51ED8AGFA 制造商:ELPIDA 制造商全稱(chēng):Elpida Memory 功能描述:512MB Unbuffered DDR2 SDRAM DIMM (64M words x 72 bits, 1 Rank)
EBE51ED8AGFA-4A-E 制造商:ELPIDA 制造商全稱(chēng):Elpida Memory 功能描述:512MB Unbuffered DDR2 SDRAM DIMM (64M words x 72 bits, 1 Rank)
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