參數(shù)資料
型號(hào)： EBE21RD4AGFA
廠商： Elpida Memory, Inc.
英文描述： LJT 24C 12#16 12#12 SKT PLUG
中文描述： 2GB的注冊(cè)DDR2 SDRAM DIMM內(nèi)存（256M字× 72位，2個(gè)等級(jí)）
文件頁(yè)數(shù)： 16/22頁(yè)
文件大?。?/td> 173K
代理商： EBE21RD4AGFA
EBE21RD4ABHA
Data Sheet E0451E20 (Ver. 2.0)
16
-5C
-4A
Frequency (Mbps)
533
400
Parameter
Symbol min.
max.
min.
max.
Unit
Notes
Active bank A to active bank B
command period
tRRD
7.5
7.5
ns
Write recovery time
Auto precharge write recovery +
precharge time
Internal write to read command delay
Internal read to precharge command
delay
Exit self refresh to a non-read command tXSNR
tWR
15
(tWR/tCK)+
(tRP/tCK)
7.5
15
(tWR/tCK)+
(tRP/tCK)
10
ns
tDAL
tCK
1
tWTR
ns
tRTP
7.5
7.5
ns
tRFC + 10
tRFC + 10
ns
Exit self refresh to a read command
Exit precharge power down to any non-
read command
Exit active power down to read
command
Exit active power down to read
command
(slow exit/low power mode)
CKE minimum pulse width (high and
low pulse width)
Output impedance test driver delay
Auto refresh to active/auto refresh
command time
Average periodic refresh interval
Minimum time clocks remains ON after
CKE asynchronously drops low
Notes: 1. For each of the terms above, if not already an integer, round to the next higher integer.
2. AL: Additive Latency.
3. MRS A12 bit defines which active power down exit timing to be applied.
4. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the
VIH(AC) level for a rising signal and VIL(AC) for a falling signal applied to the device under test.
5. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the
VIH(DC) level for a rising signal and VIL(DC) for a falling signal applied to the device under test.
CK
tXSRD
200
200
tCK
tXP
2
2
tCK
tXARD
2
2
tCK
3
tXARDS 6
AL
6
AL
tCK
2, 3
tCKE
3
3
tCK
tOIT
0
12
0
12
ns
tRFC
105
105
ns
tREFI
7.8
7.8
μ
s
tDELAY tIS + tCK + tIH
tIS + tCK + tIH
ns
DQS
/DQS
tDS
tDH
tDS
tDH
VDDQ
VIH (AC)(min.)
VIH (DC)(min.)
VREF
VIL (DC)(max.)
VIL (AC)(max.)
VSS
/CK
tIS
tIH
tIS
tIH
VDDQ
VIH (AC)(min.)
VIH (DC)(min.)
VREF
VIL (DC)(max.)
VIL (AC)(max.)
VSS
Input Waveform Timing 1 (tDS, tDH)
Input Waveform Timing 2 (tIS, tIH)
相關(guān)PDF資料
PDF描述
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EBE41RE4AAHA-4A-E Circular Connector; MIL SPEC:MIL-C-5015; Body Material:Metal; Series:GT; No. of Contacts:5; Connector Shell Size:22; Connecting Termination:Solder; Circular Shell Style:Square Flange Receptacle; Body Style:Straight
EBE41RE4AAHA-5C-E Circular Connector; MIL SPEC:MIL-C-5015; Body Material:Metal; Series:GT; No. of Contacts:5; Connector Shell Size:22; Connecting Termination:Solder; Circular Shell Style:Square Flange Receptacle; Body Style:Straight
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EBE51ED8AEFA-5C-E 512MB Unbuffered DDR2 SDRAM DIMM (64M words x 72 bits, 1 Rank)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EBE21RD4AGFA-4A-E 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:2GB Registered DDR2 SDRAM DIMM (256M words x 72 bits, 2 Ranks)
EBE21RD4AGFA-5C-E 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:2GB Registered DDR2 SDRAM DIMM (256M words x 72 bits, 2 Ranks)
EBE21RD4AGFA-6E-E 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:2GB Registered DDR2 SDRAM DIMM (256M words x 72 bits, 2 Ranks)
EBE21RD4AGFB 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:2GB Registered DDR2 SDRAM DIMM
EBE21RD4AGFB-4A-E 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:2GB Registered DDR2 SDRAM DIMM
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