106
SAM4CP [DATASHEET]
43051E–ATPL–08/14
Examples
ADD R2, R1, R3 ; Sets the flags on the result
SUBS R8, R6, #240 ; Subtracts contents of R4 from 1280
RSB R4, R4, #1280 ; Only executed if C flag set and Z
ADCHI R11, R0, R3 ; flag clear.
Multiword Arithmetic Examples
The example below shows two instructions that add a 64-bit integer contained in R2 and R3 to another 64-bit integer con-
tained in R0 and R1, and place the result in R4 and R5.
64-bit Addition Example
ADDS R4, R0, R2
ADC R5, R1, R3
; add the least significant words
; add the most significant words with carry
Multiword values do not have to use consecutive registers. The example below shows instructions that subtract a 96-bit
integer contained in R9, R1, and R11 from another contained in R6, R2, and R8. The example stores the result in R6, R9,
and R2.
96-bit Subtraction Example
SUBS
SBCS R9, R2, R1
SBC R2, R8, R11
R6, R6, R9
; subtract the least significant words
; subtract the middle words with carry
; subtract the most significant words with carry
12.6.5.2 AND, ORR, EOR, BIC, and ORN
Logical AND, OR, Exclusive OR, Bit Clear, and OR NOT.
Syntax
op
{S}{
cond
} {
Rd
,}
Rn
,
Operand2
where:
op
is one of:
AND logical AND.
ORR
logical OR, or bit set.
EOR
logical Exclusive OR.
BIC
logical AND NOT, or bit clear.
ORN
logical OR NOT.
S
is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation,
see
“Conditional Execution”
.
cond
is an optional condition code, see
“Conditional Execution”
.
Rd
is the destination register.
Rn
is the register holding the first operand.
Operand2
is a flexible second operand. See
“Flexible Second Operand”
for details of the options.
Operation
The AND, EOR, and ORR instructions perform bitwise AND, Exclusive OR, and OR operations on the values in
Rn
and
Operand2
.
The BIC instruction performs an AND operation on the bits in
Rn
with the complements of the corresponding bits in the
value of
Operand2
.
The ORN instruction performs an OR operation on the bits in
Rn
with the complements of the corresponding bits in the
value of
Operand2
.
Restrictions
Do not use SP and do not use PC.