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參數(shù)資料
| 型號(hào)： | DT28F800F3B120 |
| 廠商： | INTEL CORP |
| 元件分類(lèi)： | DRAM |
| 英文描述： | FAST BOOT BLOCK FLASH MEMORY FAMILY 8 AND 16 MBIT |
| 中文描述： | 512K X 16 FLASH 2.7V PROM, 120 ns, PDSO56 |
| 封裝： | 16 X 23.70 MM, SSOP-56 |
| 文件頁(yè)數(shù)： | 44/47頁(yè) |
| 文件大?。?/td> | 277K |
| 代理商： | DT28F800F3B120 |
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FAST BOOT BLOCK DATASHEET
E
44
PRODUCT PREVIEW
8.12
AC Characteristics
—Read-Only Operations
(1)
—
Automotive Temperature
#
Sym
Parameter
Notes
Min
Max
Unit
R1
t
CLK
CLK Period
15
ns
R2
t
CH
(t
CL
)
CLK High (Low) Time
2.5
ns
R3
t
CHCL
(t
CLCH
)
CLK Fall (Rise) Time
5
ns
R4
t
AVCH
Address Valid Setup to CLK
17
ns
R5
t
VLCH
ADV# Low Setup to CLK
17
ns
R6
t
ELCH
CE# Low Setup to CLK
17
ns
R7
t
CHQV
CLK to Output Delay
30
ns
R8
t
CHQX
Output Hold from CLK
5
ns
R9
t
CHAX
Address Hold from CLK
3
10
ns
R10
t
CHTL
(t
CHTH
)
CLK to WAIT# delay
5
30
ns
R11
t
AVVH
Address Setup to ADV# Going High
19
ns
R12
t
ELVH
CE# Low to ADV# Going High
19
ns
R13
t
AVQV
Address to Output Delay
150
ns
R14
t
ELQV
CE# Low to Output Delay
2
150
ns
R15
t
VLQV
ADV# Low to Output Delay
150
ns
R16
t
VLVH
ADV# Pulse Width
19
ns
R17
t
VHVL
ADV# Pulse Width
19
ns
R18
t
VHAX
Address Hold from ADV# Going High
3
3
ns
R19
t
APA
Page Address Access Time
35
ns
R20
t
GLQV
OE# Low to Output Delay
50
ns
R21
t
RHQV
RST# High to Output Delay
600
ns
R22
t
EHQZ
t
GHQZ
CE# or OE# High to Output in High Z,
Whichever Occurs First
4
40
ns
R23
t
OH
Output Hold from Address, CE#, or OE#
Change, Whichever Occurs First
4
0
ns
NOTES:
1.
2.
3.
4.
See AC Input/Output Reference Waveform for timing measurements and maximum allowable input slew rate.
OE# may be delayed up to t
ELQV
-t
GLQV
after the falling edge of CE# without impact on t
ELQV
.
Sampled, not 100% tested.
Output loading on WAIT# equals 15 pF.
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相關(guān)代理商/技術(shù)參數(shù) |
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| DT28F800F3B95 | 制造商:Intel 功能描述: |
| DT28F800F3T120 | 制造商:INTEL 制造商全稱(chēng):Intel Corporation 功能描述:FAST BOOT BLOCK FLASH MEMORY FAMILY 8 AND 16 MBIT |
| DT28F800F3T95 | 制造商:INTEL 功能描述:NEW 制造商:Intel 功能描述: |
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