參數(shù)資料
型號(hào)： DT28F160F3T95
廠商： INTEL CORP
元件分類： DRAM
英文描述： FAST BOOT BLOCK FLASH MEMORY FAMILY 8 AND 16 MBIT
中文描述： 1M X 16 FLASH 2.7V PROM, 95 ns, PDSO56
封裝： 16 X 23.70 MM, SSOP-56
文件頁數(shù)： 19/47頁
文件大?。?/td> 277K
代理商： DT28F160F3T95
E
FAST BOOT BLOCK DATASHEET
19
PRODUCT PREVIEW
ADV# (V)
A
19-0
(A)
Valid
Address
CLK (C)
DQ
15-0
(D/Q)
Valid
Output
DQ
15-0
(D/Q)
Valid
Output
Valid
Output
Valid
Output
Valid
Output
DQ
15-0
(D/Q)
Valid
Output
Valid
Output
Valid
Output
Valid
Output
DQ
15-0
(D/Q)
Valid
Output
Valid
Output
DQ
15-0
(D/Q)
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Code 2
Code 3
Code 4
Code 5
Code 6
Figure 5. Frequency Configuration
Table 7. Frequency Configuration Settings
(1)
Frequency
Input CLK Frequency
Configuration
Product = -90
Product = -120
Code
V
CC
= 3.0 V-3.6 V
V
CC
= 2.7 V-3.6 V
V
CC
= 2.7 V-3.6 V
1
Reserved
Reserved
Reserved
2
≤
27 MHz
≤
25 MHz
≤
20 MHz
3
≤
40 MHz
≤
33 MHz
≤
28 MHz
4
≤
54 MHz
≤
50 MHz
≤
40 MHz
5
≤
66 MHz
≤
60 MHz
≤
50 MHz
6
-
≤
66 MHz
≤
60 MHz
NOTES:
1.
Reference Section 4.1. Automotive Temperature Frequency Configuration Settings for the corresponding frequency
configuration codes to different input CLK frequencies.
4.9
Set Read Configuration
Command
The Set Read Configuration command writes data
to the read configuration register. This operation is
initiated by a two-cycle command sequence. Read
configuration setup is written, followed by a second
write that specifies the data to be written to the read
configuration register. This data is placed on the
address bus, A
15:0
, and is latched on the rising
edge of ADV#, CE#, or WE# (whichever occurs
first). The read configuration data sets the device’s
read
configuration,
burst
configuration, and burst length. The command
functions independently of the applied V
voltage.
After executing this command, the device returns to
read array mode.
order,
frequency
4.9.1
READ CONFIGURATION
The device supports two high performance read
configurations:
asynchronous
page-mode
and
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