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參數(shù)資料
| 型號(hào)： | DT28F160F3B120 |
| 廠商： | INTEL CORP |
| 元件分類： | DRAM |
| 英文描述： | FAST BOOT BLOCK FLASH MEMORY FAMILY 8 AND 16 MBIT |
| 中文描述： | 1M X 16 FLASH 2.7V PROM, 120 ns, PDSO56 |
| 封裝： | 16 X 23.70 MM, SSOP-56 |
| 文件頁數(shù)： | 27/47頁 |
| 文件大小： | 277K |
| 代理商： | DT28F160F3B120 |
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E
7.3
FAST BOOT BLOCK DATASHEET
27
PRODUCT PREVIEW
Standby Power
With CE# at a logic-high level (V
IH
) and the CUI in
read mode, the flash memory is in standby mode,
which disables much of the device’s circuitry and
substantially reduces power consumption. Outputs
(DQ
0
–DQ
15
) are placed in a high-impedance state
independent of the status of the OE# signal. If CE#
transitions to a logic-high level during erase or
program operations, the device will continue to
perform the operation and consume corresponding
active power until the operation is completed.
System engineers should analyze the breakdown of
standby time versus active time and quantify the
respective power consumption in each mode for
their specific application. This will provide a more
accurate measure of application-specific power and
energy requirements.
7.4
Power-Up/Down Operation
The device is protected against accidental block
erasure or programming during power transitions.
Power supply sequencing is not required, since
the
device is indifferent as to which power supply, V
PP
,
V
CC
, or V
CCQ
, powers-up first.
7.4.1
RST# CONNECTION
The use of RST# during system reset is important
with automated program/erase devices since the
system expects to read from the flash memory
when it comes out of reset. If a CPU reset occurs
without a flash memory reset, proper CPU
initialization will not occur because the flash
memory may be providing status information
instead of array data. Intel recommends connecting
RST# to the system reset signal to allow proper
CPU/flash initialization following system reset.
System designers must guard against spurious
writes when V
CC
voltages are above V
LKO
and V
PP
is active. Since both WE# and CE# must be low for
a command write, driving either signal to V
IH
will
inhibit writes to the device. The CUI architecture
provides additional protection since alteration of
memory contents can only occur after successful
completion of the two-step command sequences.
The device is also disabled until RST# is brought to
V
IH
, regardless of the state of its control inputs. By
holding the device in reset during power-up/down,
invalid bus conditions during power-up can be
masked, providing yet another level of memory
protection.
7.4.2
V
CC
, V
PP
AND RST# TRANSITIONS
The CUI latches commands as issued by
system
software and is not altered by V
PP
or CE#
transitions or WSM actions. Its default state upon
power-up, after exit from deep power-down mode or
after V
CC
transitions above V
LKO
(Lockout voltage),
is read array mode.
After any block erase or program operation is
complete (even after V
PP
transitions down to
V
PPLK
), the CUI must be reset to read array mode
via the Read Array command if access to the flash
memory array is desired.
7.5
Power Supply Decoupling
Flash memory’s power switching characteristics
require
careful
device
designers should consider three supply current
issues:
1.
Standby current levels (I
CCS
)
2.
Active current levels (I
CCR
)
3.
Transient peaks produced by falling and rising
edges of CE#.
decoupling.
System
Transient current magnitudes depend on the device
outputs’ capacitive and inductive loading. Two-line
control and proper decoupling capacitor selection
will suppress these transient voltage peaks. Each
flash device should have a 0.1 μF ceramic
capacitor connected between each V
CC
and GND,
and between its V
PP
and GND. These high-
frequency, inherently low-inductance capacitors
should be placed as close as possible to the
package leads.
7.5.1
V
TRACE ON PRINTED CIRCUIT
BOARDS
Designing for in-system writes to the flash memory
requires special consideration of the V
PP
power
supply trace by the printed circuit board designer.
The V
PP
pin supplies the flash memory cells current
for programming and erasing. V
PP
trace widths and
layout should be similar to that of V
CC
. Adequate
V
PP
supply traces, and decoupling capacitors
placed adjacent to the component, will decrease
spikes and overshoots.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DT28F160F3B95 | FAST BOOT BLOCK FLASH MEMORY FAMILY 8 AND 16 MBIT |
| DT28F160F3T120 | FAST BOOT BLOCK FLASH MEMORY FAMILY 8 AND 16 MBIT |
| DT28F160F3T95 | FAST BOOT BLOCK FLASH MEMORY FAMILY 8 AND 16 MBIT |
| DT28F800F3B120 | FAST BOOT BLOCK FLASH MEMORY FAMILY 8 AND 16 MBIT |
| DT28F800F3B95 | FAST BOOT BLOCK FLASH MEMORY FAMILY 8 AND 16 MBIT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DT28F160F3B95 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:FAST BOOT BLOCK FLASH MEMORY FAMILY 8 AND 16 MBIT |
| DT28F160F3T120 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:FAST BOOT BLOCK FLASH MEMORY FAMILY 8 AND 16 MBIT |
| DT28F160F3T95 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:FAST BOOT BLOCK FLASH MEMORY FAMILY 8 AND 16 MBIT |
| DT28F160S3-100 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:WORD-WIDE FlashFile MEMORY FAMILY |
| DT28F160S3-120 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:WORD-WIDE FlashFile MEMORY FAMILY |
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