參數(shù)資料
型號: DT28F016SV-080
廠商: INTEL CORP
元件分類: DRAM
英文描述: 16-MBIT (1 MBIT x 16, 2 MBIT x 8) FlashFile MEMORY
中文描述: 1M X 16 FLASH 5V PROM, 80 ns, PDSO56
封裝: 23.70 X 16 MM, SSOP-56
文件頁數(shù): 43/63頁
文件大小: 635K
代理商: DT28F016SV-080
E
5.7 Power-Up and Reset Timings
28F016SV FlashFile MEMORY
43
RP#
(P)
3/5#
(Y)
0V
3.3V
V POWER-UP
5.0V
V
CC
(3V,5V)
4.5V
PLYL
t
t
PL5V
YLPH
t
YHPH
t
Valid 5.0V Outputs
Valid
Valid
Address
(A)
Data
(Q)
Valid 3.3V Outputs
AVQV
t
AVQV
t
PHQV
t
PHQV
t
PHEL3
t
CE #
PHEL5
t
X
0528_14
Figure 14. V
CC
Power-Up and RP# Reset Waveforms
Symbol
Parameter
Notes
Min
Max
Unit
t
PLYL
t
PLYH
RP# Low to 3/5# Low (High)
0
μs
t
YLPH
t
YHPH
3/5# Low (High) to RP# High
1
2
μs
t
PL5V
t
PL3V
RP# Low to V
CC
at 4.5V minimum
(to V
CC
at 3.0V min or 3.6V max)
2
0
μs
t
PHEL3
RP# High to CE# Low (3.3V V
CC
)
1
405
ns
t
PHEL5
RP# High to CE# Low (5V V
CC
)
1
330
ns
t
AVQV
Address Valid to Data Valid for V
CC
= 5V ± 10%
3
70
ns
t
PHQV
RP# High to Data Valid for V
CC
= 5V ± 10%
3
400
ns
NOTES:
CE
0
#, CE
1
# and OE# are switched low after Power-Up.
1. The
t
and/or
t
YHPH
times must be strictly followed to guarantee all other read and program specifications for the
28F016SV.
2. The power supply may start to switch concurrently with RP# going low.
3. The address access time and RP# high to data valid time are shown for 5V V
operation of the 28F016SV-070 (Standard
Test Configuration). Refer to the AC Characteristics-Read Only Operations for 3.3V V
CC
and 5V V
CC
(High Speed Test
Configuration) values.
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