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| 型號(hào)： | DSPIC33FJ256MC510T-I/PF |
| 廠商： | Microchip Technology |
| 文件頁(yè)數(shù)： | 100/136頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DSPIC MCU/DSP 256K 100TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Asynchronous Stimulus |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | dsPIC™ 33F |
| 核心處理器： | dsPIC |
| 芯體尺寸： | 16-位 |
| 速度： | 40 MIP |
| 連通性： | CAN，I²C，IrDA，LIN，SPI，UART/USART |
| 外圍設(shè)備： | 欠壓檢測(cè)/復(fù)位，DMA，電機(jī)控制 PWM，QEI，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 85 |
| 程序存儲(chǔ)器容量： | 256KB（256K x 8） |
| 程序存儲(chǔ)器類型： | 閃存 |
| RAM 容量： | 16K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 3 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 24x10b/12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 100-TQFP |
| 包裝： | 帶卷 (TR) |
| 配用： | MA330013-ND - MODULE PLUG-IN DSPIC33 100TQFP DV164033-ND - KIT START EXPLORER 16 MPLAB ICD2 DM240001-ND - BOARD DEMO PIC24/DSPIC33/PIC32 AC164323-ND - MODULE SKT FOR 100TQFP |
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66
4235K–8051–05/08
AT89C51RD2/ED2
Figure 16-3. Full-Duplex Master-Slave Interconnection
16.3.1.1
Master Mode
The SPI operates in Master mode when the Master bit, MSTR (1), in the SPCON register is set.
Only one Master SPI device can initiate transmissions. Software begins the transmission from a
Master SPI Module by writing to the Serial Peripheral Data Register (SPDAT). If the shift register
is empty, the Byte is immediately transferred to the shift register. The Byte begins shifting out on
MOSI pin under the control of the serial clock, SCK. Simultaneously, another Byte shifts in from
the Slave on the Master’s MISO pin. The transmission ends when the Serial Peripheral transfer
data flag, SPIF, in SPSTA becomes set. At the same time that SPIF becomes set, the received
Byte from the Slave is transferred to the receive data register in SPDAT. Software clears SPIF
by reading the Serial Peripheral Status register (SPSTA) with the SPIF bit set, and then reading
the SPDAT.
16.3.1.2
Slave Mode
The SPI operates in Slave mode when the Master bit, MSTR (2), in the SPCON register is
cleared. Before a data transmission occurs, the Slave Select pin, SS, of the Slave device must
be set to ’0’. SS must remain low until the transmission is complete.
In a Slave SPI Module, data enters the shift register under the control of the SCK from the Mas-
ter SPI Module. After a Byte enters the shift register, it is immediately transferred to the receive
data register in SPDAT, and the SPIF bit is set. To prevent an overflow condition, Slave software
must then read the SPDAT before another Byte enters the shift register (3). A Slave SPI must
complete the write to the SPDAT (shift register) at least one bus cycle before the Master SPI
starts a transmission. If the write to the data register is late, the SPI transmits the data already in
the shift register from the previous transmission. The maximum SCK frequency allowed in slave
mode is F
CLK PERIPH /4.
16.3.2
Transmission Formats
Software can select any of four combinations of serial clock (SCK) phase and polarity using two
bits in the SPCON: the Clock Polarity (CPOL (4)) and the Clock Phase (CPHA4). CPOL defines
the default SCK line level in idle state. It has no significant effect on the transmission format.
CPHA defines the edges on which the input data are sampled and the edges on which the out-
put data are shifted (Figure 16-4 and Figure 16-5). The clock phase and polarity should be
identical for the Master SPI device and the communicating Slave device.
8-bit Shift register
SPI
Clock Generator
Master MCU
8-bit Shift register
MISO
MOSI
SCK
VSS
VDD
SS
Slave MCU
1.
The SPI Module should be configured as a Master before it is enabled (SPEN set). Also, the Mas-
ter SPI should be configured before the Slave SPI.
2.
The SPI Module should be configured as a Slave before it is enabled (SPEN set).
3.
The maximum frequency of the SCK for an SPI configured as a Slave is the bus clock speed.
4.
Before writing to the CPOL and CPHA bits, the SPI should be disabled (SPEN = ’0’).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| dsPIC33FJ256MC710A-E/PF | 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC 16Bit 40MIPS 256KB Flash RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| dsPIC33FJ256MC710A-E/PT | 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC 16Bit 40MIPS 256KB Flash RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| dsPIC33FJ256MC710A-H/PF | 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC 16B MCU 40MIPS 256KB FLASH RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| dsPIC33FJ256MC710A-H/PT | 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC 16B MCU 40MIPS 256KB FLASH RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| DSPIC33FJ256MC710A-I/P | 制造商:Microchip Technology Inc 功能描述:DSP, Motor Control:Flash Memory, 16-Bit, 40MIPS, 30750 RAM Bytes, TQFP-100 |
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