參數(shù)資料
型號(hào): DSPIC33FJ128GP710-I/PT
廠商: Microchip Technology
文件頁(yè)數(shù): 31/90頁(yè)
文件大小: 0K
描述: IC DSPIC MCU/DSP 128K 100TQFP
產(chǎn)品培訓(xùn)模塊: dsPIC33F DMAC
Introduction to dsPIC33F Architecture Part 1
Asynchronous Stimulus
Introduction to dsPIC33F Architecture Part 2
特色產(chǎn)品: PIC24FJ/33FJ MCUs & dsPIC? DSCs
標(biāo)準(zhǔn)包裝: 119
系列: dsPIC™ 33F
核心處理器: dsPIC
芯體尺寸: 16-位
速度: 40 MIP
連通性: CAN,I²C,IrDA,LIN,SPI,UART/USART
外圍設(shè)備: AC'97,欠壓檢測(cè)/復(fù)位,DMA,I²S,POR,PWM,WDT
輸入/輸出數(shù): 85
程序存儲(chǔ)器容量: 128KB(128K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 16K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 32x10b/12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 100-TQFP
包裝: 托盤
產(chǎn)品目錄頁(yè)面: 654 (CN2011-ZH PDF)
配用: 876-1001-ND - DSPIC33 BREAKOUT BOARD
AC164333-ND - MODULE SKT FOR PM3 100QFP
DM300024-ND - KIT DEMO DSPICDEM 1.1
DV164033-ND - KIT START EXPLORER 16 MPLAB ICD2
MA330012-ND - MODULE DSPIC33 100P TO 84QFP
MA330011-ND - MODULE DSPIC33 100P TO 100QFP
DM240001-ND - BOARD DEMO PIC24/DSPIC33/PIC32
DV164005-ND - KIT ICD2 SIMPLE SUIT W/USB CABLE
2005 Microchip Technology Inc.
Preliminary
DS70155C-page 35
dsPIC33F
TABLE 9-4:
MATH INSTRUCTIONS
Assembly
Syntax
Description
Words
Cycles
ADD
f {,WREG}
Destination = f + WREG
1
ADD
#lit10,Wn
Wn = lit10 + Wn
1
ADD
Wb,#lit5,Wd
Wd = Wb + lit5
1
ADD
Wb,Ws,Wd
Wd = Wb + Ws
1
ADDC
f {,WREG}
Destination = f + WREG + (C)
1
ADDC
#lit10,Wn
Wn = lit10 + Wn + (C)
1
ADDC
Wb,#lit5,Wd
Wd = Wb + lit5 + (C)
1
ADDC
Wb,Ws,Wd
Wd = Wb + Ws + (C)
1
DAW.B
Wn
Wn = decimal adjust Wn
1
DEC
f {,WREG}
Destination = f – 1
1
DEC
Ws,Wd
Wd = Ws – 1
1
DEC2
f {,WREG}
Destination = f – 2
1
DEC2
Ws,Wd
Wd = Ws – 2
1
DIV.S
Wm,Wn
Signed 16/16-bit integer divide*
118
DIV.SD
Wm,Wn
Signed 32/16-bit integer divide*
118
DIV.U
Wm,Wn
Unsigned 16/16-bit integer divide*
118
DIV.UD
Wm,Wn
Unsigned 32/16-bit integer divide*
118
DIVF
Wm,Wn
Signed 16/16-bit fractional divide*
118
INC
f {,WREG}
Destination = f + 1
1
INC
Ws,Wd
Wd = Ws + 1
1
INC2
f {,WREG}
Destination = f + 2
1
INC2
Ws,Wd
Wd = Ws + 2
1
MUL
f
W3:W2 = f * WREG
1
MUL.SS
Wb,Ws,Wnd
{Wnd + 1,Wnd} = sign(Wb) * sign(Ws)
1
MUL.SU
Wb,#lit5,Wnd
{Wnd + 1,Wnd} = sign(Wb) * unsign(lit5)
1
MUL.SU
Wb,Ws,Wnd
{Wnd + 1,Wnd} = sign(Wb) * unsign(Ws)
1
MUL.US
Wb,Ws,Wnd
{Wnd + 1,Wnd} = unsign(Wb) * sign(Ws)
1
MUL.UU
Wb,#lit5,Wnd
{Wnd + 1,Wnd} = unsign(Wb) * unsign(lit5)
1
MUL.UU
Wb,Ws,Wnd
{Wnd + 1,Wnd} = unsign(Wb) * unsign(Ws)
1
SE
Ws,Wnd
Wnd = sign-extended Ws
1
SUB
f {,WREG}
Destination = f – WREG
1
SUB
#lit10, Wn
Wn = Wn – lit10
1
SUB
Wb,#lit5,Wd
Wd = Wb – lit5
1
SUB
Wb,Ws,Wd
Wd = Wb – Ws
1
SUBB
f {,WREG}
Destination = f – WREG – (C)
1
SUBB
#lit10, Wn
Wn = Wn – lit10 – (C)
1
SUBB
Wb,#lit5,Wd
Wd = Wb – lit5 – (C)1
1
SUBB
Wb,Ws,Wd
Wd = Wb – Ws – (C)1
1
SUBBR
f {,WREG}
Destination = WREG – f – (C)1
1
SUBBR
Wb,#lit5,Wd
Wd = lit5 – Wb – (C)1
1
SUBBR
Wb,Ws,Wd
Wd = Ws – Wb – (C)1
1
SUBR
f {,WREG}
Destination = WREG – f
1
SUBR
Wb,#lit5,Wd
Wd = lit5 – Wb
1
SUBR
Wb,Ws,Wd
Wd = Ws – Wb
1
ZE
Ws,Wnd
Wnd = zero-extended Ws
1
* Divide instructions are interruptible on a cycle-by-cycle basis. Also, divide instructions must be accompanied by a
REPEAT
instruction, which adds 1 extra cycle.
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