參數(shù)資料
型號: DSPIC30F3014-20I/ML
廠商: Microchip Technology
文件頁數(shù): 138/153頁
文件大?。?/td> 0K
描述: IC DSPIC MCU/DSP 24K 44QFN
產(chǎn)品培訓模塊: Serial Communications using dsPIC30F I2C
Serial Communications using dsPIC30F SPI
Serial Communications using dsPIC30F UART
dsPIC30F 12 bit ADC - Part 2
dsPIC30F Addressing Modes - Part 1
dsPIC30F Architecture - Part 1
dsPIC30F DSP Engine & ALU
dsPIC30F Interrupts
dsPIC30F Motor Control PWM
dsPIC Timers
Asynchronous Stimulus
dsPIC30F Addressing Modes - Part 2
dsPIC30F Architecture - Part 2
dsPIC30F 12-bit ADC Part 1
標準包裝: 45
系列: dsPIC™ 30F
核心處理器: dsPIC
芯體尺寸: 16-位
速度: 20 MIPS
連通性: I²C,SPI,UART/USART
外圍設備: 欠壓檢測/復位,POR,PWM,WDT
輸入/輸出數(shù): 30
程序存儲器容量: 24KB(8K x 24)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 1K x 8
RAM 容量: 2K x 8
電壓 - 電源 (Vcc/Vdd): 2.5 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 13x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-VQFN 裸露焊盤
包裝: 管件
配用: XLT44QFN2-ND - SOCKET TRAN ICE 44QFN/40DIP
AC164322-ND - MODULE SOCKET MPLAB PM3 28/44QFN
其它名稱: DSPIC30F301420IML
2010 Microchip Technology Inc.
DS70138G-page 85
dsPIC30F3014/4013
13.0
OUTPUT COMPARE MODULE
This section describes the output compare module and
associated operational modes. The features provided
by this module are useful in applications requiring
operational modes, such as:
Generation of Variable Width Output Pulses
Power Factor Correction
Figure 13-1 depicts a block diagram of the output
compare module.
The key operational features of the output compare
module include:
Timer2 and Timer3 Selection mode
Simple Output Compare Match mode
Dual Output Compare Match mode
Simple PWM mode
Output Compare During Sleep and Idle modes
Interrupt on Output Compare/PWM Event
These operating modes are determined by setting the
appropriate bits in the 16-bit OCxCON SFR (where
x = 1,2,3,...,N). The dsPIC DSC devices contain up to
8 compare channels (i.e., the maximum value of N is 8).
The dsPIC30F3014 device contains
2 compare
channels while the dsPIC30F4013 device contains
4 compare channels.
OCxRS and OCxR in Figure 13-1 represent the Dual
Compare registers. In the Dual Compare mode, the
OCxR register is used for the first compare and OCxRS
is used for the second compare.
13.1
Timer2 and Timer3 Selection Mode
Each output compare channel can select between one
of two 16-bit timers: Timer2 or Timer3.
The selection of the timers is controlled by the OCTSEL
bit (OCxCON<3>). Timer2 is the default timer resource
for the output compare module.
FIGURE 13-1:
OUTPUT COMPARE MODE BLOCK DIAGRAM
Note:
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals,
register
descriptions
and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046).
OCxR
Comparator
Output
Logic
Q
S
R
OCM<2:0>
Output
OCx
Set Flag bit
OCxIF
OCxRS
Mode Select
3
Note:
Where ‘x’ is shown, reference is made to the registers associated with the respective output compare
channels, 1 through N.
OCFA
OCTSEL
01
T2P2_MATCH
TMR2<15:0
TMR3<15:0>
T3P3_MATCH
From GP
(for x = 1, 2, 3 or 4)
or OCFB
(for x = 5, 6, 7 or 8)
01
Timer Module
Enable
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