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| 型號： | DSPCOMMANDUM |
| 英文描述： | Universal Command Converter for DSP User＇s Manual |
| 中文描述： | 通用命令轉換為數(shù)字信號處理器用戶手冊 |
| 文件頁數(shù)： | 40/70頁 |
| 文件大小： | 550K |
| 代理商： | DSPCOMMANDUM |
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3-8
Universal Command Converter
Motorola
Host Computer Hardware
Figure 3-6. Multiple JTAG Target Connections
3.1.7 TCK Drive and Timing Considerations
The signals from the command converter are TDO, TCK and TMS, and TRST. Signal
TCK requires fast rise and fall times dictated by the TCK pin timing specification, and
consequently attention must be given to the drive capabilities of the circuits driving this
signals. There is no problem with TDO, as each TDO output is connected to only one TDI
input. TMS need only be valid at the rising edge of TCK, similarly there is no problem
with TRST as the reset signal is not subject to the timing constraints of TCK.
There is a potential problem with driving the TCK circuit with a large number of target
devices. The problem is related to the rise and fall times of TCK, caused by excessive
capacitance, which can cause communication problems with a single circuit connecting
multiple TCK input pins.
Acceptable transition times may be achieved for TCK by driving no more than four JTAG
inputs from each buffered output. This may be achieved with two configurations.
Figure 3-6 shows one method. Here (in effect) one signalling connects each of the TCK
inputs. A buffer is placed in the circuit after each fourth input, at most, to restore the signal
quality for subsequent inputs. The propagation delay of the buffer is not significant.
Figure 3-7 shows another possible configuration which also enables signal quality to meet
the requirements. In this configuration the signal is split and buffered into a number of
parallel TCKn signals. Each of these signals may drive up to 4 TCK inputs.
TDI
TCK TMS
TDO
TDI
TCK TMS
TDO
TDI
TCK TMS
TDO
TDI
TCK TMS
TDO
TDI
TCK TMS
TDO
TDI
TCK TMS
TDO
TCK
TMS
TDO
TDI
MAXIMUM OF 4 LOADS ON
TCK CIRCUITS
BUFFER—74HCT244
OR SIMILAR
RESET
TRST
AA1950
TRST RESET
TRST RESET
TRST RESET
TRST RESET
TRST RESET
TRST RESET
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