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參數(shù)資料
| 型號(hào)： | DSPB56725AF |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 4/48頁 |
| 文件大?。?/td> | 0K |
| 描述： | DSP 24BIT AUD 250MHZ 80-LQFP |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | DSP56K/Symphony |
| 類型： | 音頻處理器 |
| 接口： | 主機(jī)接口，I²C，SAI，SPI |
| 時(shí)鐘速率： | 250MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 112kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.20V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 80-LQFP |
| 供應(yīng)商設(shè)備封裝： | 80-LQFP（14x14） |
| 包裝： | 托盤 |
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Symphony DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 2
Freescale Semiconductor
12
19
Duration of level sensitive IRQA assertion to ensure interrupt
service (when exiting Stop)1, 2, 3
PLL is active during Stop and Stop delay is enabled (OMR Bit
6 = 0)
(128 Kbytes
× TC)
655
—
μs
PLL is active during Stop and Stop delay is not enabled (OMR
Bit 6 = 1)
25
× TC
125
—
ns
PLL is not active during Stop and Stop delay is enabled (OMR
Bit 6 = 0)
(128KxTC) + PLLLOCK
855
—
μs
PLL is not active during Stop and Stop delay is not enabled
(OMR Bit 6 = 1)
(25
× TC) + PLLLOCK
200
—
μs
20
Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to
general-purpose transfer output valid caused by first interrupt
instruction execution1
10
× TC + 3.8
—
53.8
ns
21
Interrupt Requests Rate1
ESAI, ESAI_1, ESAI_2, ESAI_3, SHI, SHI_1, Timer, Timer_1
12
× TC
—
60.0
ns
DMA
8
× TC
—
40.0
ns
IRQ, NMI (edge trigger)
8
× TC
—
40.0
ns
IRQ (level trigger)
12
× TC
—
60.0
ns
22
DMA Requests Rate
Data read from ESAI, ESAI_1, ESAI_2, ESAI_3, SHI, SHI_1
6
× TC
—
30.0
ns
Data write to ESAI, ESAI_1, ESAI_2, ESAI_3, SHI, SHI_1
7
× TC
—
35.0
ns
Timer, Timer_1
2
× TC
—
10.0
ns
IRQ, NMI (edge trigger)
3
× TC
—
15.0
ns
Note:
1. When using fast interrupts and when IRQA, IRQB, IRQC, and IRQD are defined as level-sensitive, timings 19 through 21 apply
to prevent multiple interrupt service. To avoid these timing restrictions, the Edge-triggered mode is recommended when using
fast interrupts. Long interrupts are recommended when using Level-sensitive mode.
2. For PLL disable, if using an external clock (PCTL Bit 13 = 1), no stabilization delay is required and recovery time will be defined
by the OMR Bit 6 settings.
For PLL enable, (if bit 12 of the PCTL register is 0), the PLL is shut down during Stop. Recovering from Stop requires the PLL
to get locked. The PLL lock procedure duration, PLL Lock Cycles (PLC), may be in the range of 200 us.
3. Periodically sampled and not 100% tested.
4. RESET duration is measured during the time in which RESET is asserted, VDD is valid, and the EXTAL input is active and
valid. When VDD is valid, but the other “required RESET duration” conditions (as specified above) have not been yet met, the
device circuitry will be in an uninitialized state that can result in significant power consumption and heat-up. Designs should
minimize this state to the shortest possible duration.
Table 7. Reset, Stop, Mode Select, and Interrupt Timing (Continued)
No.
Characteristics
Expression
Min
Max
Unit
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