Symphony DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 2 Freescale Semico" />
參數(shù)資料
型號(hào)： DSPB56725AF
廠商： Freescale Semiconductor
文件頁數(shù)： 3/48頁
文件大?。?/td> 0K
描述： DSP 24BIT AUD 250MHZ 80-LQFP
標(biāo)準(zhǔn)包裝： 90
系列： DSP56K/Symphony
類型： 音頻處理器
接口： 主機(jī)接口，I²C，SAI，SPI
時(shí)鐘速率： 250MHz
非易失內(nèi)存： 外部
芯片上RAM： 112kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.20V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 80-LQFP
供應(yīng)商設(shè)備封裝： 80-LQFP（14x14）
包裝： 托盤
Symphony DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 2
Freescale Semiconductor
11
Table 6 lists the clock operation.
1.1.9
Reset, Stop, Mode Select, and Interrupt Timing
Table 7 lists the reset, stop, mode select, and interrupt timing.
Table 6. Clock Operation
No.
Characteristics
Symbol
Min
Max
Units
6
EXTAL input high 1
(40% to 60% duty cycle)
Crystal oscillator
Square wave input
Eth
16.67
2.5
100
inf
ns
7
EXTAL input low1
(40% to 60% duty cycle)
Crystal oscillator
Square wave input
Etl
16.67
2.5
100
inf
ns
8
EXTAL cycle time
With PLL disabled
With PLL enabled
Etc
5
33.3
inf
500
ns
9
Instruction cycle time
With PLL disabled
With PLL enabled
Tc
5
44
inf
5120
ns
Note:
1. Measured at 50% of the input transition.
2. The indicated duty cycle is for the specified maximum frequency for which a part is rated. The minimum clock high or low time
required for correct operation, however, remains the same at lower operating frequencies; therefore, when a lower clock
frequency is used, the signal symmetry may vary from the specified duty cycle as long as the minimum high time and low
time requirements are met.
3. Maximum frequency of 200 MHz supported at 0.95 V < VVDD_CORE < 1.05 V and –40 < Tj < 100° C
Maximum frequency of 250 MHz supported at 1.14 V < VVDD_CORE < 1.26 V and 0 < Tj < 90° C
4. PLLLOCK = 200 μs.
Table 7. Reset, Stop, Mode Select, and Interrupt Timing
No.
Characteristics
Expression
Min
Max
Unit
10
Delay from RESET assertion to all pins at reset value3
——
11
ns
11
Required RESET duration4
Power on, external clock generator, PLL disabled
Power on, external clock generator, PLL enabled
2
× TC
10
—
ns
2
× TC
10
—
ns
13
Syn reset deassert delay time
Minimum
2
× TC
10
—
ns
Maximum (PLL enabled)
(2xTC)+PLLLOCK
200
—
us
14
Mode select setup time
—
10
—
ns
15
Mode select hold time
—
12
—
ns
16
Minimum edge-triggered interrupt request assertion width
—
7
—
ns
17
Minimum edge-triggered interrupt request deassertion width
—
4
—
ns
18
Delay from interrupt trigger to interrupt code execution
10
× TC + 4
54
—
ns
相關(guān)PDF資料
PDF描述
HCM06DSAS CONN EDGECARD 12POS R/A .156 SLD
VI-B6L-CY-F2 CONVERTER MOD DC/DC 28V 50W
MAX6690YMEE+ IC TEMP SENSOR SMBUS 16-QSOP
DSPB56721AF AUDIO PROCESSOR SYMPH 80-LQFP
ESM43DRYI CONN EDGECARD 86POS DIP .156 SLD
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DSPB56725CAF 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC PB FREE DSPB56724 AP RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
DSPB720DB1E 功能描述:子卡和OEM板 B VERSION 720 DAUGHTER C RoHS:否 制造商:BeagleBoard by CircuitCo 產(chǎn)品:BeagleBone LCD4 Boards 用于:BeagleBone - BB-Bone - Open Source Development Kit
DSPB721DB1E 功能描述:子卡和OEM板 B VERSION 721 DAUGHTER C RoHS:否 制造商:BeagleBoard by CircuitCo 產(chǎn)品:BeagleBone LCD4 Boards 用于:BeagleBone - BB-Bone - Open Source Development Kit
DSPB721DB2E 功能描述:子卡和OEM板 B VERSION 721 Daughter C RoHS:否 制造商:BeagleBoard by CircuitCo 產(chǎn)品:BeagleBone LCD4 Boards 用于:BeagleBone - BB-Bone - Open Source Development Kit
DSPB724DB1E 功能描述:子卡和OEM板 B VERSION 724 Daughter C RoHS:否 制造商:BeagleBoard by CircuitCo 產(chǎn)品:BeagleBone LCD4 Boards 用于:BeagleBone - BB-Bone - Open Source Development Kit
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*