參數(shù)資料
型號: DSPB56007FJ88
英文描述: DSP|24-BIT|CMOS|QFP|80PIN|PLASTIC
中文描述: 數(shù)字信號處理器| 24位|的CMOS | QFP封裝| 80腳|塑料
文件頁數(shù): 4/83頁
文件大?。?/td> 382K
代理商: DSPB56007FJ88
iv
DSP56007/D
MOTOROLA
DSP56007
Features
Peripheral and Support Circuits
Serial Audio Interface (SAI) includes two receivers and three transmitters,
master or slave capability, implementation of I
protocols; and two sets of SAI interrupt vectors
2
S, Sony, and Matsushita audio
Serial Host Interface (SHI) features single master capability, 10-word receive
FIFO, and support for 8-, 16-, and 24-bit words
External Memory Interface (EMI), implemented as a peripheral supporting:
Page-mode DRAMs (one or two chips): 64 K
and 4 M
×
4 bits
×
4, 256 K
×
4,
SRAMs (one to four): 256 K
×
8 bits
Data bus may be 4 or 8 bits wide
Data words may be 8, 12, 16, 20, or 24 bits wide
Four dedicated, independent, programmable General Purpose Input/ Output
(GPIO) lines
On-chip peripheral registers memory mapped in data memory space
Three external interrupt request pins
On-Chip Emulation (OnCE) port for unobtrusive, processor speed-
independent debugging
Software-programmable, Phase Lock Loop-based (PLL) frequency synthesizer
for the core clock
Power-saving Wait and Stop modes
Fully static, HCMOS design for operating frequencies down to DC
80-pin plastic Quad Flat Pack surface-mount package; 14
(2.15–2.45 mm range); 0.65 mm lead pitch
×
14
×
2.20 mm
Complete pinout compatibility between DSP56009, DSP56004,
DSP56004ROM, and DSP56007 for easy upgrades
5 V power supply
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