參數(shù)資料
型號(hào)： DSPA56721AF
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors
中文描述： SymphonyTM DSP56720 / DSP56721多核音頻處理器
文件頁(yè)數(shù)： 37/54頁(yè)
文件大?。?/td> 671K
代理商： DSPA56721AF
Symphony
TM
DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
Freescale Semiconductor
37
339
Delay from write data strobe deassertion to
host request assertion for “Last Data Register” write
4, 7, 9
2
×
T
C
10.0
–
ns
340
Delay from data strobe assertion to
host request deassertion for “Last Data Register” read or write (HROD =
0)
4, 8, 9
–
–
19.1
ns
341
Delay from data strobe assertion to
host request deassertion for “Last Data Register” read or write (HROD =
1, open drain Host Request)
4, 8, 9, 10
–
–
300.0
ns
342
Delay from DMA HACK deassertion to HOREQ assertion
For “Last Data Register” read
4
For “Last Data Register” write
4
ns
2
×
T
C
+ 19.1
29.1
–
1
×
T
C
+ 19.1
24.1
–
For other cases
–
0.0
–
343
Delay from DMA HACK assertion to HOREQ deassertion
HROD = 0
4
–
–
20.2
ns
344
Delay from DMA HACK assertion to HOREQ deassertion for “Last Data
Register” read or write
HROD = 1, open drain Host Request
4, 10
–
–
300.0
ns
Notes:
1.
2.
3.
4.
5.
In the timing diagrams that follow, the controls pins are drawn as active low. The pin polarity is programmable.
V
CC
= 1.0 V ± 10%; T
J
=
–40°C to +125°C; C
L
= 50 pF.
The read data strobe is HRD in the dual data strobe mode and HDS in the single data strobe mode.
The “l(fā)ast data register” is the register at address $7, which is the last location to be read or written in data transfers.
This timing is applicable only if a read from the “l(fā)ast data register” is followed by a read from the RXL, RXM, or RXH registers without
first polling RXDF or HREQ bits, or waiting for the assertion of the HOREQ signal.
This timing is applicable only if two consecutive reads from one of these registers are executed.
The write data strobe is HWR in the dual data strobe mode and HDS in the single data strobe mode.
The data strobe is host read (HRD) or host write (HWR) in the dual data strobe mode and host data strobe (HDS) in the single data
strobe mode.
The host request is HOREQ in the single host request mode and HRRQ and HTRQ in the double host request mode.
10. In this calculation, the host request signal is pulled up by a 4.7 kW resistor in the open-drain mode.
11. HDI24_1 specs match those of HDI24.
6.
7.
8.
9.
Table 18. HDI24 Timing Parameters (Continued)
No.
Characteristics
2
Expression
200 MHz
Unit
Min
Max
相關(guān)PDF資料
PDF描述
DSPA56721AG SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors
DSPB56720AG SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors
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DSPB56721AG SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors
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相關(guān)代理商/技術(shù)參數(shù)
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