參數(shù)資料
型號: DSP56F803BU80E
廠商: Freescale Semiconductor
文件頁數(shù): 40/52頁
文件大小: 0K
描述: IC DSP 80MHZ 64KB FLASH 100LQFP
特色產(chǎn)品: DSP56F803 Digital Signal Controller
標(biāo)準(zhǔn)包裝: 90
系列: 56F8xx
核心處理器: 56800
芯體尺寸: 16-位
速度: 80MHz
連通性: CAN,EBI/EMI,SCI,SPI
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 16
程序存儲器容量: 71KB(35.5K x 16)
程序存儲器類型: 閃存
RAM 容量: 2.5K x 16
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x12b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 100-LQFP
包裝: 托盤
Controller Area Network (CAN) Timing
56F803 Technical Data, Rev. 16
Freescale Semiconductor
45
Figure 3-27 Bus Wakeup Detection
1.
If Wakeup glitch filter is enabled during the design initialization and also CAN is put into SLEEP mode then, any bus event
(on MSCAN_RX pin) whose duration is less than 5 micro seconds is filtered away. However, a valid CAN bus wakeup detec-
tion takes place for a wakeup pulse equal to or greater than 5 microseconds. The value of 5 microseconds originates from the
fact that the CAN wakeup message consists of 5 dominant bits at the highest possible baud rate of 1Mbps.
2.
Parameters listed are guaranteed by design.
MSCAN_RX
CAN receive
data pin
(Input)
T WAKEUP
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