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5685X Digital Signal Controller User Manual, Rev. 4
Freescale Semiconductor
xx
3-12
Direct Memory Access 5 Register Address Map
(DMA5_BASE = $1FFEE8) see Chapter 9 . . . . . . . . . . . . . . . . . . . . . . . . 3-13
Serial Communication Interface 0 Registers Address Map
(SCI0_BASE = $1FFFE0) see Chapter 10. . . . . . . . . . . . . . . . . . . . . . . . . 3-14
Serial Communication Interface 1 Registers Address Map
(SCI1_BASE = $1FFDF8) see Chapter 10 . . . . . . . . . . . . . . . . . . . . . . . . 3-14
Serial Peripheral Interface Registers Address Map
(SPI_BASE =$1FFFE8) see Chapter 11 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
Enhanced Synchronous Serial Interface 0 Registers Address Map
(ESSI0_BASE = $1FFE20) see Chapter 12. . . . . . . . . . . . . . . . . . . . . . . . 3-15
Enhanced Synchronous Serial Interface 1 Registers Address Map
(ESSI1_BASE =$1FFE00) see Chapter 12 . . . . . . . . . . . . . . . . . . . . . . . . 3-15
Quad Timer Registers Address Map
(TMR_BASE = $1FFE80) see Chapter 13. . . . . . . . . . . . . . . . . . . . . . . . . 3-16
Time-Of-Day Registers Address Map
(TOD_BASE = $1FFFC0) see Chapter 14. . . . . . . . . . . . . . . . . . . . . . . . . 3-16
General Purpose Input/Output A Register Map
(GPIOA_BASE = $1FFE60) see Chapter 15 . . . . . . . . . . . . . . . . . . . . . . . 3-16
General Purpose Input/Output B Register Map
(GPIOB_BASE = $1FFE64) see Chapter 15 . . . . . . . . . . . . . . . . . . . . . . . 3-17
General Purpose Input/Output C Register Map
(GPIOC_BASE = $1FFE68) see Chapter 15 . . . . . . . . . . . . . . . . . . . . . . . 3-17
General Purpose Input/Output D Register Map
(GPIOD_BASE = $1FFE6C) see Chapter 15. . . . . . . . . . . . . . . . . . . . . . . 3-17
General Purpose Input/Output E Register Map
(GPIOE_BASE = $1FFE70) see Chapter 15 . . . . . . . . . . . . . . . . . . . . . . 3-17
General Purpose Input/Output F Register Map
(GPIOF_BASE = $1FFE74) see Chapter 15. . . . . . . . . . . . . . . . . . . . . . . 3-18
General Purpose Input/Output G Register Map
(GPIOG_BASE = $1FFE78) see Chapter 15. . . . . . . . . . . . . . . . . . . . . . . 3-18
General Purpose Input/Output H Register Map
(GPIOH_BASE = $1FFE7C) see Chapter 15 . . . . . . . . . . . . . . . . . . . . . . 3-18
Host Interface 8 Registers
(HI8_BASE =$1FFFD8) see Chapter 16 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18
IPBus Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
Clock Generator Inputs/Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
Reset Generator Inputs/Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
Register Inputs/Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
Power Mode Control Inputs/Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
Derived Clock Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
System Integration Module Memory Map (SIM_BASE = $1FFF08) . . . . . . . . . . . . 4-8
3-13
3-14
3-15
3-16
3-17
3-18
3-19
3-20
3-21
3-22
3-23
3-24
3-25
3-26
3-27
3-28
4-1
4-2
4-3
4-4
4-5
4-6
4-7