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LIST OF FIGURES
List of Figures, Rev. 4
Freescale Semiconductor
xv
1-1
1-2
1-3
1-4
1-5
1-6
1-7
1-8
56853 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
56854 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
56855 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
56857 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
56858 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
56800E Chip Architecture with External Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
56800E Core Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16
IPBus Bridge Interface With Other Main Components
System Side Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-24
Register Programming Model for the 5685x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-35
56853 Signals Identified by Functional Group2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
56854 Signals Identified by Functional Group2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
56855 Signals Identified by Functional Group2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
56857 Signals Identified by Functional Group2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
56858 Signals Identified by Functional Group2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
56853 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
56854 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
56855 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
56857 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
56858 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
System Integration Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
SIM Register Map Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
EMI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
EMI Register Map Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
Data Bus Contention Timing Requiring MDAR Field Assertion . . . . . . . . . . . . . . 5-12
External Read Cycle with Clock and RWS = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
External Read Cycle with RWS = 1, RWSH = 0 and RWSS = 0 . . . . . . . . . . . . . 5-15
External Read Cycle with RWSS = RWS = 1, and RWSH = 0 . . . . . . . . . . . . . . . 5-16
External Read Cycle RWS = RWSH = 1 and RWSS = 0 . . . . . . . . . . . . . . . . . . . 5-17
External Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18
External Write Cycle with WWS = 1, WWSH = 0, and WWSS = 0 . . . . . . . . . . . . 5-19
External Write Cycle with WWSS = 1, WWS = 0 and WWSH = 0 . . . . . . . . . . . . 5-20
External Write Cycle with WWS = 0, WWSH = 1, WWSS = 0 . . . . . . . . . . . . . . . 5-21
External Write Cycle with WWSS = WWS = 1 and WWSH = 0 . . . . . . . . . . . . . . 5-22
External Write Cycle with WWS = WWSH = 1 (WWSS = 0). . . . . . . . . . . . . . . . . 5-23
OCCS Integration Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
1-9
2-1
2-2
2-3
2-4
2-5
3-1
3-2
3-3
3-4
3-5
4-1
4-2
5-1
5-2
5-6
5-8
5-9
5-10
5-11
5-12
5-13
5-14
5-15
5-16
5-17
6-1