參數(shù)資料
型號(hào)： DSP56855BUE
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： 16-bit Digital Signal Controllers
中文描述： 16位數(shù)字信號(hào)控制器
文件頁(yè)數(shù)： 17/52頁(yè)
文件大?。?/td> 618K
代理商： DSP56855BUE
General Characteristics
56855 Technical Data, Rev. 6
Freescale Semiconductor
17
Part 4 Specifications
4.1 General Characteristics
The 56855 is fabricated in high-density CMOS with 5-volt tolerant TTL-compatible digital inputs. The
term “5-volt tolerant” refers to the capability of an I/O pin, built on a 3.3V compatible process
technology, to withstand a voltage up to 5.5V without damaging the device. Many systems have a
mixture of devices designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V
and 5V- compatible I/O voltage levels (a standard 3.3V I/O is designed to receive a maximum voltage of
3.3V
±
10% during normal operation without causing damage). This 5V tolerant capability therefore
offers the power savings of 3.3V I/O levels while being able to receive 5V levels without being damaged.
Absolute maximum ratings given in
Table 4-1
are stress ratings only, and functional operation at the
maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent
damage to the device.
The 56855 DC/AC electrical specifications are preliminary and are from design simulations. These
specifications may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized
41
TMS
Input
Test Mode Select Input (TMS)
—This input pin is used to sequence the
JTAG TAP controller’s state machine. It is sampled on the rising edge of
TCK and has an on-chip pull-up resistor.
Note:
Always tie the TMS pin to V
DD
through a 2.2K resistor.
38
TRST
Input
Test Reset (TRST)
—As an input, a low signal on this pin provides a reset
signal to the JTAG TAP controller. To ensure complete hardware reset,
TRST should be asserted whenever RESET is asserted. The only
exception occurs in a debugging environment, since the Enhanced
OnCE/JTAG module is under the control of the debugger. In this case it is
not necessary to assert TRST when asserting RESET. Outside of a
debugging environment RESET should be permanently asserted by
grounding the signal, thus disabling the Enhanced OnCE/JTAG module on
the device.
Note:
used in a debugging environment, TRST may be tied to V
SS
through a 1K resistor.
For normal operation, connect TRST directly to V
SS
. If the design is to be
37
DE
Input
/Output
Debug Event (DE)
—This is an open-drain, bidirectional, active low signal.
As an input, it is a means of entering debug mode of operation from an
external command controller. As an output, it is a means of acknowledging
that the chip has entered debug mode.
This pin is connected internally to a weak pull-up resistor.
Table 3-1. 56855 Signal and Package Information for the 100-pin LQFP (Continued)
Pin No.
Signal Name
Type
Description
相關(guān)PDF資料
PDF描述
DSP56855E 16-bit Digital Signal Controllers
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DSP56855E 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers
DSP56855PB 制造商:未知廠家 制造商全稱:未知廠家 功能描述:56855 Digital Signal Processor Product Brief
DSP56856 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Digitial Signal Controller
DSP56857 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers
DSP56857BU120 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC 120Mhz/120MIPS RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
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