56855 Technical Data, Rev. 6
16
Freescale Semiconductor
91
SC00
GPIOC3
Input
/Output
Input/Output
ESSI Serial Control Pin 0 (SC00)
—The function of this pin is determined
by the selection of either synchronous or asynchronous mode. For
asynchronous mode, this pin will be used for the receive clock I/O. For
synchronous mode, this pin is used either for transmitter1 output or for
serial I/O flag 0.
Port C GPIO (3)
—This pin is a General Purpose I/O (GPIO) pin when the
ESSI is not in use.
92
SC01
GPIOC4
Input
/Output
Input/Output
ESSI Serial Control Pin 1 (SC01)
—The function of this pin is determined
by the selection of either synchronous or asynchronous mode. For
asynchronous mode, this pin is the receiver frame sync I/O. For
synchronous mode, this pin is used either for transmitter2 output or for
serial I/O flag 1.
Port C GPIO (4)
—This pin is a General Purpose I/O (GPIO) pin when the
ESSI is not in use.
93
SC02
GPIOC5
Input
/Output
Input or Output
ESSI Serial Control Pin 2 (SC02)
—This pin is used for frame sync I/O.
SC02 is the frame sync for both the transmitter and receiver in synchronous
mode and for the transmitter only in asynchronous mode. When configured
as an output, this pin is the internally generated frame sync signal. When
configured as an input, this pin receives an external frame sync signal for
the transmitter (and the receiver in synchronous operation).
Port C GPIO (5)
—This pin is a General Purpose I/O (GPIO) pin when the
ESSI is not in use.
20
XTAL
Input/
Output
Crystal Oscillator Output (XTAL)
—This output connects the internal
crystal oscillator output to an external crystal. If an external clock source
other than a crystal oscillator is used, XTAL must be used as the input.
21
EXTAL
Input
External Crystal Oscillator Input (EXTAL)
—This input should be
connected to an external crystal. If an external clock source other than a
crystal oscillator is used, EXTAL must be tied off. See
Section 4.5.2
26
CLKO
Output
Clock Output (CLKO)
—This pin outputs a buffered clock signal. When
enabled, this signal is the system clock divided by four.
42
TCK
Input
Test Clock Input (TCK)
—This input pin provides a gated clock to
synchronize the test logic and to shift serial data to the JTAG/Enhanced
OnCE port. The pin is connected internally to a pull-down resistor.
40
TDI
Input
Test Data Input (TDI)
—This input pin provides a serial input data stream to
the JTAG/Enhanced OnCE port. It is sampled on the rising edge of TCK
and has an on-chip pull-up resistor.
39
TDO
Output (Z)
Test Data Output (TDO)
—This tri-statable output pin provides a serial
output data stream from the JTAG/Enhanced OnCE port. It is driven in the
Shift-IR and Shift-DR controller states, and changes on the falling edge of
TCK.
Table 3-1. 56855 Signal and Package Information for the 100-pin LQFP (Continued)
Pin No.
Signal Name
Type
Description