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參數(shù)資料
| 型號(hào)： | DSP201 |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | 16-bit fixed point DSP with Flash |
| 中文描述： | 具有閃存的 16 位定點(diǎn) DSP |
| 文件頁(yè)數(shù)： | 7/19頁(yè) |
| 文件大?。?/td> | 106K |
| 代理商： | DSP201 |
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DSP201/202
7
THEORY OF OPERATION
The DSP201 and DSP202 are basic voltage output digital-
to-analog converters with complete logic interface circuitry
for ease of use with standard digital signal processing ICs.
Data words are transmitted from the DSP IC on its serial
port, leaving the DSP IC parallel ports free for digital
communication.
The DSP201 and DSP202 are pipelined internally. When the
user gives a convert command at time t, two actions are
initiated. First, the data stored in the internal shift registers
following the previous convert command (at t – 1) is used to
update the output D/A converters immediately. Second, the
DSP201 or DSP202 transmits a synchronization pulse to the
DSP IC and starts clocking new data into the shift register
using the system Bit Clock. This data is then used to update
the D/As when the t + 1 convert command is received.
Both the DSP201 and DSP202 are 18-bit D/As internally.
On-chip logic can be programmed to use 18-bits of data to
update the D/A outputs, or can be programmed to update the
D/A based on 16-bit data words. Additionally, the logic in
the DSP202 can accept a 32-bit data word (the Cascade
Mode), and update both D/A channels simultaneously with
16 bits each. All of these modes can be hard-wired or logic-
controlled externally, so that no extra overhead on the part
of the DSP IC is required.
In the 16-bit modes, the DSP201 and DSP202 will append
zeros to the 16-bits transferred to each of the internal D/As,
which are full 18-bit converters. The 18-bit word-length
mode can be used with DSP ICs programmed for either 24-
bit or 32-bit output words, in which case the DSP201 or
DSP202 will clock in the first 18-bits of data after the
synchronization pulse, and ignore additional information on
the serial line. When programmed to accept 16-bit words,
the DSP201 and DSP202 can be used with DSP ICs pro-
grammed to output 16-, 24-, or 32-bit words, and will ignore
additional information after the first 16 bits on the serial line.
The DSP201 and DSP202 are complete voltage output D/A
converters, with on-chip references and output amplifiers to
drive
±
3V into 375
loads. State-of-the-art bipolar tech-
nologies are used in the D/A section to maximize the output
update rate, to maximize dynamic performance, and to
eliminate glitch problems. Advanced plastic packaging meth-
ods makes this performance attainable economically.
BASIC OPERATION
DATA FORMAT AND OUTPUT LEVELS
The DSP201 and DSP202 accept serial data, MSB first, in
standard Binary Two’s Complement format. The length of
the data words can be selected as shown below, and the
D/A output level generated by a specific input code is shown
in Table I.
As with all standard D/As, the output ranges from negative
full scale (–3V) to 1 LSB below positive full scale (+3V –
1LSB). The bipolar output amplifiers are designed to drive
375
loads at full speed and accuracy.
UPDATING THE OUTPUT
With ENABLE (pin 17) LOW, the falling edge of a Convert
Command arriving on CONV (pin 15) will immediately
update the D/A outputs with the data stored in the internal
shift registers following the previous Convert Command.
The Convert Command can be asynchronous to any other
signals or clocks without reducing accuracy, although sys-
tem accuracy is often enhanced by synchronizing digital
signals.
For a full-scale change in the input code, the output will
typically settle to within
±
0.006% of its final level within
2.5
μ
s. The slew rate of the output amplifier is typically 15V/
μ
s, for a full power bandwidth close to 800kHz. All of the
specifications and typical performance curves are achieved
with a full 400kHz update rate, unless otherwise specified.
The DSP201 and DSP202 are guaranteed operational to a
full 500kHz update rate, which exceeds the maximum Bit
Clock rate for most standard DSP ICs.
DATA TRANSFER
Data is transmitted serially to the DSP201 or DSP202, and
is clocked into the internal shift registers on the rising edge
of the external Data Transfer Clock or Bit Clock (XCLK
input on pin 12.) This clock can be as fast as 12MHz. The
Data Transfer Clock can tolerate duty cycles from 40% to
60%.
As indicated in the timing diagrams in Figure 1, either 16-
or 18-bits of data will be clocked into the DSP201 or
DSP202, or 32-bits will be clocked into the DSP202 in the
INPUT CODE
OUTPUT VOLTAGE
16-BIT MODE AND
DSP202 CASCADE MODE
HEX
16-BIT MODE AND
DSP202 CASCADE MODE
BINARY
18-BIT MODE
18-BIT MODE
0111...1111
0000...0000
1111...1111
1000...0000
7FFF
0000
FFFF
8000
1FFFF
00000
3FFFF
20000
+2.999908V
0V
–92
μ
V
–3.000000V
2.999977V
0V
–23
μ
V
–3.000000V
Theoretical LSB Size
91.6
μ
V
22.9
μ
V
TABLE I. Output Voltage vs Input Code.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DSP201JP | 16-bit fixed point DSP with Flash |
| DSP201KP | 16-bit fixed point DSP with Flash |
| DSP202 | 16-bit fixed point DSP with Flash |
| DSP202JP | 16-bit fixed point DSP with Flash |
| DSP202KP | 16-bit fixed point DSP with Flash |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DSP-201 | 制造商:SYNERGY 制造商全稱:SYNERGY MICROWAVE CORPORATION 功能描述:POWER DIVIDERS 0ì : 2-WAY |
| DSP201/DSP202 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP201. DSP202 - DISCONTINUED PRODUCT. No longer recommended for new design. |
| DSP201JP | 制造商:BB 制造商全稱:BB 功能描述:DSP-Compatible Single/Dual DIGITAL-TO-ANALOG CONVERTERS |
| DSP201KP | 制造商:BB 制造商全稱:BB 功能描述:DSP-Compatible Single/Dual DIGITAL-TO-ANALOG CONVERTERS |
| DSP-201M | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:DIA SURGE SUPPRESSOR (DSS) |
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