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參數(shù)資料
| 型號： | DSP201 |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 16-bit fixed point DSP with Flash |
| 中文描述： | 具有閃存的 16 位定點 DSP |
| 文件頁數(shù)： | 2/19頁 |
| 文件大小： | 106K |
| 代理商： | DSP201 |
DSP201/202
2
SPECIFICATIONS
ELECTRICAL
T
A
= 0
°
C to 70
°
C, Output Update Frequency, f
S
, = 400kHz, V
A
+ = V
D
+ = +5V, V
A
– = V
D
– = –5V, unless otherwise specified.
DSP201JP
DSP202JP
DSP201KP
DSP202KP
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
RESOLUTION
18
*
Bits
DYNAMIC RANGE
108
*
dB
ANALOG OUTPUT
Voltage Range
Impedance
Current
Slew Rate
Settling Time to 0.006%
for Full-Scale Step
R
L
= 375
±
3
0.1
±
8
15
2.5
*
V
mA
V/
μ
s
μ
s
*
*
*
*
R
L
= 375
R
L
= 1.5k
, C
L
= 100pF
R
L
= 1.5k
, C
L
= 100pF
THROUGHPUT SPEED
(1)
Update Rate
DSP202 in Cascade Mode
CASC = LOW on DSP202
CASC = HIGH
500
300
*
kHz
kHz
AC ACCURACY
(2, 3)
Signal to (Noise + Distortion) Ratio
f
OUT
= 1kHz
f
OUT
= 1kHz (–60dB)
f
OUT
= 10kHz
f
= 1kHz
f
OUT
= 1kHz to 100kHz
82
86
30
86
–90
105
88
90
32
90
–92
*
dB
(4)
dB
dB
dB
dB
80
86
Total Harmonic Distortion
Channel Separation
on DSP202
–85
–88
DC ACCURACY
Integral Nonlinearity Error
Differential Nonlinearity Error
Bipolar Zero Error
(5)
Bipolar Zero Error Drift
Bipolar Zero Mismatch
(5)
Gain Error
Gain Error Drift
Gain Error Mismatch
Digital Feedthrough
Power Supply Sensitivity
±
0.006
±
0.006
±
10
20
5
1
100
1
–105
–60
–60
±
0.004
±
0.004
*
*
*
*
*
*
*
*
*
%
%
mV
ppm FSR/
°
C
mV
%
ppm/
°
C
%
dB
dB
dB
DSP202 Channels
3
*
DSP202 Channels
ENABLE = HIGH
–5.1 < V
A
–, V
D
– < –4.9
+4.9 <V
A
+, V
D
+ < +5.1
3
*
DIGITAL INPUTS
Format
Coding
Logic Levels
V
IL
V
Data Transfer Clock
Frequency
Duty Cycle
Serial; MSB first; 16/18-bit and Cascaded
Binary Twos Complement
I
IL
=
±
10
μ
A
I
IH
=
±
10
μ
A
0
+0.8
+5
*
*
*
*
V
V
+2.4
12
60
*
*
*
*
MHz
%
40
50
*
DIGITAL OUTPUTS
V
OL
V
OH
I
OL
= 4mA
I
OH
= 4mA
0
+0.4
+5
*
*
*
*
V
V
+2.4
POWER SUPPLIES
Rated Voltage
V
A
+
V
A
–
V
D
+
V
D
–
Current
I
A
+
I
A
–
I
D
+
I
D
–
Power Consumption
+4.75
–5.25
+4.75
–5.25
+5
–5
+5
–5
+5.25
–4.75
+5.25
–4.75
*
*
*
*
*
*
*
*
*
*
*
*
V
V
V
V
18
17
13
25
365
*
*
*
*
*
mA
mA
mA
mA
mW
450
*
TEMPERATURE RANGE
Specification
Storage
0
+70
+125
*
*
*
*
o
C
o
C
–40
NOTES: (1) The data transfer clock must be at least 24 times the update rate for the standard mode, and 40 times the update rate in the DSP202 Cascade Mode.
(2) All dynamic specifications are based on 2048-point FFTs. (3) Data for the 1kHz test is bandlimited to 0 to 20kHz. Data for the 10kHz test is bandlimited to 0 to
40kHz. (4) All specifications in dB are referred to a full-scale output,
±
3Vp-p. (5) Adjustable to zero with external potentiometer.
相關PDF資料 |
PDF描述 |
|---|---|
| DSP201JP | 16-bit fixed point DSP with Flash |
| DSP201KP | 16-bit fixed point DSP with Flash |
| DSP202 | 16-bit fixed point DSP with Flash |
| DSP202JP | 16-bit fixed point DSP with Flash |
| DSP202KP | 16-bit fixed point DSP with Flash |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| DSP-201 | 制造商:SYNERGY 制造商全稱:SYNERGY MICROWAVE CORPORATION 功能描述:POWER DIVIDERS 0ì : 2-WAY |
| DSP201/DSP202 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP201. DSP202 - DISCONTINUED PRODUCT. No longer recommended for new design. |
| DSP201JP | 制造商:BB 制造商全稱:BB 功能描述:DSP-Compatible Single/Dual DIGITAL-TO-ANALOG CONVERTERS |
| DSP201KP | 制造商:BB 制造商全稱:BB 功能描述:DSP-Compatible Single/Dual DIGITAL-TO-ANALOG CONVERTERS |
| DSP-201M | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:DIA SURGE SUPPRESSOR (DSS) |
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