參數(shù)資料
型號： DSD1793
英文描述： DIODE, SMT SCHOTTKY 3A 60V SK36 SMC
中文描述： 24位192千赫采樣高級分段音頻立體聲數(shù)模轉(zhuǎn)換器
文件頁數(shù)： 7/47頁
文件大?。?/td> 428K
代理商： DSD1793
DSD1793
SLES075A MARCH 2003 REVISED JANUARY 2004
www.ti.com
15
SYSTEM CLOCK AND RESET FUNCTIONS
System Clock Input
The DSD1793 requires a system clock for operating the digital interpolation filters and advanced segment DAC
modulators. The system clock is applied at the SCK input (pin 5). The DSD1793 has a system clock detection circuit
that automatically senses which frequency the system clock is operating. Table 1 shows examples of system clock
frequencies for common audio sampling rates. If the oversampling rate of the delta-sigma modulator is selected as
128 fS, the system clock frequency is over 256 fS.
Figure 24 shows the timing requirements for the system clock input. For optimal performance, it is important to use
a clock source with low phase jitter and noise. One of the Texas Instruments PLL1700 family of multiclock generators
is an excellent choice for providing the DSD1793 system clock.
Table 1. System Clock Rates for Common Audio Sampling Frequencies
SAMPLING FREQUENCY
SYSTEM CLOCK FREQUENCY (FSCK) (MHZ)
SAMPLING FREQUENCY
128 fS
192 fS
256 fS
384 fS
512 fS
768 fS
32 kHz
4.096 (1)
6.144 (1)
8.192
12.288
16.384
24.576
44.1 kHz
5.6488 (1)
8.4672
11.2896
16.9344
22.5792
33.8688
48 kHz
6.144 (1)
9.216
12.288
18.432
24.576
36.864
96 kHz
12.288
18.432
24.576
36.864
49.152 (1)
73.728 (1)
192 kHz
24.576
36.864
49.152 (1)
73.728 (1)
(2)
(1) This system clock rate is not supported in I2C fast mode.
(2) This system clock rate is not supported for the given sampling frequency.
t(SCKH)
System Clock (SCK)
t(SCKL)
2.0 V
0.8 V
H
L
t(SCY)
PARAMETERS
MIN
MAX
UNITS
t(SCY)
System clock pulse cycle time
13
ns
t(SCKH) System clock pulse duration, HIGH
5
ns
t(SCKL) System clock pulse duration, LOW
5
ns
Figure 24. System Clock Input Timing
Power-On Reset Function
The DSD1793 includes a power-on reset function. Figure 25 shows the operation of this function. With VDD > 2 V,
the power-on reset function is enabled. The initialization sequence requires 1024 system clocks from the time
VDD > 2 V. After the initialization period, the DSD1793 is set to its default reset state, as described in the MODE
CONTROL REGISTERS section of this data sheet.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DSD1793DB 功能描述:音頻數(shù)/模轉(zhuǎn)換器 IC 24-Bit 192kHz Smplng Adv Stg Stereo DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量: 分辨率:16 bit 接口類型:I2S, UBS 轉(zhuǎn)換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數(shù)量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel
DSD1793DBG4 功能描述:音頻數(shù)/模轉(zhuǎn)換器 IC 24B 192kHz Sampl Adv Segment Aud St DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量: 分辨率:16 bit 接口類型:I2S, UBS 轉(zhuǎn)換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數(shù)量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel
DSD1793DBR 功能描述:音頻數(shù)/模轉(zhuǎn)換器 IC 24-Bit 192kHz Smplng Adv Stg Stereo DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量: 分辨率:16 bit 接口類型:I2S, UBS 轉(zhuǎn)換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數(shù)量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel
DSD1793DBRG4 功能描述:音頻數(shù)/模轉(zhuǎn)換器 IC 24-Bit 192kHz Smplng Adv Stg Stereo DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量: 分辨率:16 bit 接口類型:I2S, UBS 轉(zhuǎn)換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數(shù)量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel
DSD1794 制造商:TI 制造商全稱:Texas Instruments 功能描述:24-BIT, 192-kHz SAMPLING, ADVANCED SEGMENT, AUDIO STRRO DIGITAL-TO-ALALOG CONVERTER
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