參數(shù)資料
型號(hào)： DSD1792DBG4
廠商： Texas Instruments
文件頁(yè)數(shù)： 37/57頁(yè)
文件大小： 0K
描述： IC 24BIT STEREO AUD DAC 28-SSOP
產(chǎn)品培訓(xùn)模塊： Data Converter Basics
標(biāo)準(zhǔn)包裝： 47
位數(shù)： 24
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 2
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 335mW
工作溫度： -25°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 28-SSOP（0.209"，5.30mm 寬）
供應(yīng)商設(shè)備封裝： 28-SSOP
包裝： 管件
輸出數(shù)目和類型： 4 電流，單極
采樣率（每秒）： 200k
DSD1792
SLES067B MARCH 2003 REVISED NOVEMBER 2006
www.ti.com
42
TDMCA Format
The DSD1792 supports the time-division-multiplexed command and audio (TDMCA) data format to simplify the
host control serial interface. The TDMCA format is designed not only for the McBSP of TI DSPs but also for
any programmable devices. The TDMCA format can transfer not only audio data but also command data, so
that it can be used together with any kind of device that supports the TDMCA format. The TDMCA frame
consists of command field, extended command field, and some audio data fields. Those audio data are
transported to IN devices (such as a DAC) and/or from OUT devices (such as an ADC). The DSD1792 is an
IN device. LRCK and BCK are used with both IN and OUT devices so that the sample frequency of all devices
in a system must be the same. The TDMCA mode supports a maximum of 30 device IDs. The maximum number
of audio channels depends on the BCK frequency.
TDMCA Mode Determination
The DSD1792 recognizes the TDMCA mode automatically when it receives an LRCK signal with a pulse
duration of two BCK clocks. If the TDMCA mode operation is not needed, the duty cycle of LRCK must be 50%.
Figure 51 shows the LRCK and BCK timing that determines the TDMCA mode. The DSD1792 enters the
TDMCA mode after two continuous TDMCA frames. Any TDMCA commands can be issued during the next
TDMCA frame after the TDMCA mode is entered.
Pre-TDMCA Frame
BCK
LRCK
2 BCK
TDMCA Frame
Command
Accept
Figure 51. LRCK and BCK Timing of Determination TDMCA Mode
TDMCA Terminals
TDMCA requires six signals, of which four signals are for command and audio data interface, and two pairs of
signals which are for daisy chaining. Those signals can be shared as in the following table. The DO signal has
a 3-state output so that it can be connected directly to other devices.
TERMINAL
NAME
TDMCA
NAME
I/O
DESCRIPTION
PLRCK
LRCK
I
TDMCA frame start signal. It must be the same as the sampling frequency.
PBCK
BCK
I
TDMCA clock. Its frequency must be high enough to communicate a TDMCA frame within an LRCK cycle.
PDATA
DI
I
TDMCA command and audio data input signal
MDO
DO
O
TDMCA command data 3-state output signal
MC
DCI
I
TDMCA daisy-chain input signal
MS
DCO
O
TDMCA daisy-chain output signal
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