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參數(shù)資料
| 型號(hào)： | DS90CR217MTD/NOPB |
| 廠商： | National Semiconductor |
| 文件頁(yè)數(shù)： | 17/18頁(yè) |
| 文件大小： | 0K |
| 描述： | IC TXRX 21BIT CHAN LINK 48TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Interconnect Solutions for LVDS Applications |
| 標(biāo)準(zhǔn)包裝： | 38 |
| 類(lèi)型： | 發(fā)射器 |
| 驅(qū)動(dòng)器/接收器數(shù)： | 21/3 |
| 規(guī)程： | LVDS |
| 電源電壓： | 3 V ~ 3.6 V |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 48-TFSOP（0.240"，6.10mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 48-TSSOP |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁(yè)面： | 1280 (CN2011-ZH PDF) |
| 其它名稱： | *DS90CR217MTD *DS90CR217MTD/NOPB DS90CR217MTD |
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SNLS226A – OCTOBER 2006 – REVISED FEBRUARY 2013
APPLICATIONS INFORMATION
Table 1. DS90CR217 PIN DESCRIPTIONS — CHANNEL LINK TRANSMITTER
Pin Name
I/O
No.
Description
TxIN
I
21
TTL level input.
TxOUT+
O
3
Positive LVDS differential data output.
TxOUT
O
3
Negative LVDS differential data output.
TxCLK IN
I
1
TTL level clock input. The rising edge acts as data strobe. Pin name TxCLK IN.
TxCLK OUT+
O
1
Positive LVDS differential clock output.
TxCLK OUT
O
1
Negative LVDS differential clock output.
PWR DWN
I
1
TTL level input. Assertion (low input) TRI-STATEs the outputs, ensuring low current at power down. See
Applications Information section.
VCC
I
4
Power supply pins for TTL inputs.
GND
I
5
Ground pins for TTL inputs.
PLL VCC
I
1
Power supply pins for PLL.
PLL GND
I
2
Ground pins for PLL.
LVDS VCC
I
1
Power supply pin for LVDS outputs.
LVDS GND
I
3
Ground pins for LVDS outputs.
The Channel Link devices are intended to be used in a wide variety of data transmission applications. Depending
upon the application the interconnecting media may vary. For example, for lower data rate (clock rate) and
shorter cable lengths (< 2m), the media electrical performance is less critical. For higher speed/long distance
applications the media's performance becomes more critical. Certain cable constructions provide tighter skew
(matched electrical length between the conductors and pairs). Twin-coax for example, has been demonstrated at
distances as great as 5 meters and with the maximum data transfer of 1.785 Gbit/s. Additional applications
information can be found in the following Interface Application Notes:
AN = ####
Topic
AN-1041 (SNLA218)
Introduction to Channel Link
AN-1108 (SNLA008)
Channel Link PCB and Interconnect Design-In Guidelines
AN-1109 (SNLA220)
Multi-Drop Channel-Link Operation
AN-806 (SNLA026)
Transmission Line Theory
AN-905 (SNLA035)
Transmission Line Calculations and Differential Impedance
AN-916 (SNLA219)
Cable Information
CABLES
A cable interface between the transmitter and receiver needs to support the differential LVDS pairs. The ideal
cable/connector interface would have a constant 100
Ω differential impedance throughout the path. It is also
recommended that cable skew remain below 90ps (@ 85 MHz clock rate) to maintain a sufficient data sampling
window at the receiver.
In addition to the four or five cable pairs that carry data and clock, it is recommended to provide at least one
additional conductor (or pair) which connects ground between the transmitter and receiver. This low impedance
ground provides a common-mode return path for the two devices. Some of the more commonly used cable types
for point-to-point applications include flat ribbon, flex, twisted pair and Twin-Coax. All are available in a variety of
configurations and options. Flat ribbon cable, flex and twisted pair generally perform well in short point-to-point
applications while Twin-Coax is good for short and long applications. When using ribbon cable, it is
recommended to place a ground line between each differential pair to act as a barrier to noise coupling between
adjacent pairs. For Twin-Coax cable applications, it is recommended to utilize a shield on each cable pair. All
extended point-to-point applications should also employ an overall shield surrounding all cable pairs regardless
of the cable type. This overall shield results in improved transmission parameters such as faster attainable
speeds, longer distances between transmitter and receiver and reduced problems associated with EMS or EMI.
8
Copyright 2006–2013, Texas Instruments Incorporated
Product Folder Links: DS90CR217
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS90CR217MTDX | 功能描述:串行器/解串器 - Serdes RoHS:否 制造商:Texas Instruments 類(lèi)型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類(lèi)型:ECL/LVDS 輸出類(lèi)型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| DS90CR217MTDX/NOPB | 功能描述:串行器/解串器 - Serdes RoHS:否 制造商:Texas Instruments 類(lèi)型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類(lèi)型:ECL/LVDS 輸出類(lèi)型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| DS90CR218 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:+3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link Receiver - 75 MHz |
| DS90CR218A | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:+3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link - 85 MHz |
| DS90CR218A_06 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:+3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link - 12 MHz to 85 MHz |
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