參數(shù)資料
型號: DS89C440-QNG
廠商: Maxim Integrated Products
文件頁數(shù): 27/46頁
文件大?。?/td> 0K
描述: IC MCU FLASH 32KB 25MHZ 44-PLCC
標(biāo)準(zhǔn)包裝: 26
系列: 89C
核心處理器: 8051
芯體尺寸: 8-位
速度: 25MHz
連通性: EBI/EMI,SIO,UART/USART
外圍設(shè)備: 電源故障復(fù)位,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 32KB(32K x 8)
程序存儲器類型: 閃存
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-LCC(J 形引線)
包裝: 管件
DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers
33 of 46
Table 10. Page Mode 2, Data Memory Cycle Stretch Values (PAGES1:PAGES0 = 11)
RD/WR
PULSE WIDTH (IN NUMBER OF OSCILLATOR CLOCKS)
MD2:MD0
STRETCH
CYCLES
4X/2X, CD1,
CD0 = 100
4X/2X, CD1,
CD0 = 000
4X/2X, CD1,
CD0 = X10
4X/2X, CD1,
CD0 = X11
000
0
0.5
1
2
2048
001
1
2
4
4096
010
2
4
8
8192
011
3
6
12
12,288
100
7
4
8
16
16,384
101
8
5
10
20
20,480
110
9
6
12
24
24,576
111
10
7
14
28
28,672
As shown in the previous tables, the stretch feature supports eight stretched external data-memory access options,
which can be categorized into three timing groups. When the stretch value is cleared to 000b, there is no stretch on
external data memory access, and a MOVX instruction is completed in two basic memory cycles. When the stretch
value is set to 1, 2, or 3, the external data memory access is extended by 1, 2, or 3 stretch memory cycles,
respectively. Note that the first stretch value does not result in adding four system clocks to the control signals. This
is because the first stretch uses one system clock to create additional address setup and data bus float time and
one system clock to create additional address and data hold time. When using very slow RAM and peripherals, a
larger stretch value (4–7) can be selected. In this stretch category, two stretch cycles are used to create additional
setup (the ALE pulse width is also stretched by one stretch cycle for page miss) and one stretch cycle is used to
create additional hold time. The following timing diagrams illustrate the external data memory access at divide-by-1
system clock mode (CD1:CD0 = 10b).
Figure 12 illustrates the external data-memory stretch-cycle timing relationship when PAGEE = 1 and
PAGES1:PAGES0 = 01. The stretch cycle shown is for a stretch value of 1 and is coincident with a page miss.
Note that the first stretch value does not result in adding four system clocks to the RD/WR control signals. This is
because the first stretch uses one system clock to create additional setup and one system clock to create
additional hold time.
Figure 13 shows the timing relationship for a slow peripheral interface (stretch value = 4). Note that a page hit data
memory cycle is shorter than a page miss data memory cycle. The ALE pulse width is also stretched by a stretch
cycle in the case of a page miss.
The stretched data memory bus cycle timing relationship for PAGES = 11 is identical to nonpage mode operation
since the basic data memory cycle always contains four system clocks in this page mode operation.
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DS89C440-QNL 功能描述:IC MCU FLASH 32KB 33MHZ 44-PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器, 系列:89C 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:260 系列:73S12xx 核心處理器:80515 芯體尺寸:8-位 速度:24MHz 連通性:I²C,智能卡,UART/USART,USB 外圍設(shè)備:LED,POR,WDT 輸入/輸出數(shù):9 程序存儲器容量:64KB(64K x 8) 程序存儲器類型:閃存 EEPROM 大小:- RAM 容量:2K x 8 電壓 - 電源 (Vcc/Vdd):2.7 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:- 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:68-VFQFN 裸露焊盤 包裝:管件
DS89C440-QNL+ 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:Ultra-High-Speed Flash Microcontrollers
DS89C440-XXX 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:Ultra-High-Speed Flash Microcontrollers
DS89C450 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:Ultra-High-Speed Flash Microcontrollers
DS89C450+ENG 制造商:Maxim Integrated Products 功能描述:MCU 8BIT CISC 64KB FLASH 5V 44TQFP - Trays