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參數(shù)資料
| 型號： | DS87C550-QNL |
| 英文描述： | EPROM High-Speed Micro with A/D and PWM |
| 中文描述： | 存儲器高速微與A / D及PWM |
| 文件頁數(shù)： | 8/50頁 |
| 文件大?。?/td> | 763K |
| 代理商： | DS87C550-QNL |
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DS87C550
8 of 50
instruction used two machine cycles or 24 oscillator cycles. Therefore, they required the same amount of
time. In the DS87C550, the MOVX instruction takes as little as two machine cycles or eight oscillator
cycles, but the “MOV direct, direct” uses three machine cycles or 12 oscillator cycles. While both are
faster than their original counterparts, they now have different execution times. This is because the
DS87C550 usually uses one instruction cycle for each instruction byte. Examine the timing of each
instruction for familiarity with the changes. Note that a machine cycle now requires just 4 clocks, and
provides one ALE pulse per cycle. Many instructions require only one cycle, but some require five. In the
original architecture, all were one or two cycles except for MUL and DIV. Refer to the High Speed Micro
User’s Guide for details and individual instruction timing.
SPECIAL FUNCTION REGISTERS
Special Function Registers (SFRs) control most special features of the DS87C550. This allows the
DS87C550 to have many new features but use the same instruction set as the 8051. When writing
software to use a new feature, an equate statement defines the SFR to an assembler or compiler. This is
the only change needed to access the new function. The DS87C550 duplicates the SFRs contained in the
standard 80C52. Table 2 shows the register addresses and bit locations. Many are standard 80C52
registers. The High Speed Micro User’s Guide describes all SFRs in full detail.
SPECIAL FUNCTION REGISTER LOCATION:
Table 2
REGISTER
BIT7
BIT6
PORT0
P0.7
P0.6
SP
DPL
DPH
DPL1
DPH1
DPS
ID1
ID0
PCON
SMOD_0
SMOD0
OFDF
TCON
TF1
TR1
TMOD
GATE
C/
T
TL0
TL1
TH0
TH1
CKCON
WD1
WD0
T2M
PORT1
P1.7
P1.6
RCON
-
-
SCON0
SM0/FE_0
SM1_0
SM2_0
SBUF0
PMR
CD1
CD0
SWB
PORT2
P2.7
P2.6
SADDR0
SADDR1
IE
EA
EAD
CMPL0
CMPL1
CMPL2
CPTL0
CPTL1
CPTL2
CPTL3
PORT3
P3.7
P3.6
ADCON1
STRT/BSY
EOC
CONT/SS
BIT5
P0.5
BIT4
P0.4
BIT3
P0.3
BIT2
P0.2
BIT1
P0.1
BIT0
P0.0
ADDRESS
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
90h
91h
98h
99h
9Fh
A0h
A1h
A2h
A8h
A9h
AAh
ABh
ACh
ADh
AEh
AFh
B0h
B2h
TSL
-
-
-
-
SEL
IDLE
IT0
M0
OFDE
TR0
M0
GF1
IE1
GATE
GF0
IT1
C/
T
STOP
IE0
M1
TF0
M1
T1M
P1.4
-
REN_0
T0M
P1.3
CKRDY
TB8_0
MD2
P1.2
RGMD
RB8_0
MD1
P1.1
RGSL
TI_0
MD0
P1.0
BGS
RI_0
P1.5
-
CTM
P2.4
4X/
2X
P2.3
ALEOFF
P2.2
DEM1
P2.1
DME0
P2.0
P2.5
ES1
ES0
ET1
EX1
ET0
EX0
P3.5
P3.4
ADEX
P3.3
WCQ
P3.2
WCM
P3.1
ADON
P3.0
WCIO
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