參數(shù)資料
型號(hào)： DS87C550-QNL
英文描述： EPROM High-Speed Micro with A/D and PWM
中文描述： 存儲(chǔ)器高速微與A / D及PWM
文件頁(yè)數(shù)： 22/50頁(yè)
文件大小： 763K
代理商： DS87C550-QNL
DS87C550
22 of 50
Specifications section). This reference voltage may be selected to be either an internal band-gap voltage
(VBG) or an external reference (Avref+, Avref-). This selection is made by writing a 0 (uses internal
reference VBG) or writing a 1 (uses external reference (Avref+, Avref-) to the ADRS bit (PWMADR.7).
The default reset condition is for the internal reference to be selected.
Selecting a single analog signal for conversion is achieved by software writing the desired channel
number (0 through 7) into SFR bits MUX2 through MUX0 bits of the A/D Control Register 2
(ADCON2.6-4). The single output of the multiplexer is then provided to a sample and hold circuit that
maintains a steady signal during the conversion process.
A/D CONVERSION PROCESS
The A/D conversion process can be configured for one-shot or continuous mode operation. For one-shot
operation, the SFR bit CONT/SS (ADCON1.5) must be a 0. The conversion process is then initiated by
software writing a 1 to the STRT/BSY SFR bit (ADCON1.7) if the ADEX (ADCON1.4) bit is a 0. If the
ADEX bit is a 1, then the conversion is initiated by an active low signal on the external pin STADC
(P6.7). If continuous mode is selected (CONT/SS = 1), then the first conversion is initiated as described
above, but another conversion will be automatically started at the completion of the previous conversion.
Once initiated, the conversion process requires 16 A/D clock periods (T
ACLK
) to complete. Because of the
dynamic nature of the converter, the A/D clock period can be no less that 1 us and no more than 6.25 us.
This requirement is expressed as follows:
1.0 us <= T
ACLK
<= 6.25 us
Therefore any single conversion time can range from 16 us minimum to 100 us maximum, depending on
the selected A/D clock frequency.
The A/D clock frequency is a function of the processor’s machine cycle clock and the A/D clock’s
prescaler setting as shown by the following equation:
T
ACLK
= T
MCLK
* (N+1)
where N is the prescaler setting in APS3:0.
The processor’s machine cycle clock period (T
MCLK
) is normally the external crystal (or oscillator)
frequency multiplied by 4 (but can be affected by the CD1, CD0, and 4X/
2X
bits). The A/D clock period
must be set by the user to ensure that it falls within the minimum and maximum values specified above.
As an example, assume the processor’s crystal frequency is 33 MHz and that the processor is running in a
standard divide-by-4 mode. This means that the period of the processors machine cycle clock, i.e.,
T
MCLK
, will be (1/33 MHz)*4 or 121.2 ns. If it is assumed that the application requires the fastest possible
conversion time, then the desired T
ACLK
is 1.0 us. The necessary prescale value can then be calculated as:
N = (T
ACLK
/T
MCLK
)-1
Therefore for this example, N = 7.25. Since N must be an integer, the value of N must be 8 (rounded up
to the next integer). This results in a conversion clock T
ACLK
= 1.091 us.
The prescaler value must be stored in SFR bits APS3 through APS0 (ADCON2.3-0) to achieve the proper
A/D clock. These bits default to 0 on a processor reset, so they must be set as desired by the processor’s
initialization software.
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