參數(shù)資料
型號: DS87C520-WCL
英文描述: EPROM/ROM High-Speed Micro
中文描述: 存儲器/ ROM的高速微
文件頁數(shù): 35/45頁
文件大?。?/td> 1415K
代理商: DS87C520-WCL
DS87C520/DS83C520 EPROM/ROM High-Speed Microcontrollers
35 of 45
EXPLANATION OF AC SYMBOLS
In an effort to remain compatible with the original 8051 family, the DS87C520 and DS83C520 specify
the same parameters as such devices, using the same symbols. For completeness, the following is an
explanation of the symbols.
t
Time
A
Address
C
Clock
D
Input data
H
Logic level high
L
Logic level low
POWER-CYCLE TIMING CHARACTERISTICS
I
P
Q
R
V
Instruction
PSEN
Output data
RD
signal
Valid
W
X
WR
signal
No longer a valid logic
level
Tri-State
Z
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Cycle Startup Time
Power-On Reset Delay
t
CSU
t
POR
1.8
ms
t
CLCL
1
2
65,536
Note 1:
Startup time for crystals varies with load capacitance and manufacturer. Time shown is for an 11.0592MHz crystal
manufactured by Fox.
Reset delay is a synchronous counter of crystal oscillations after crystal startup. Counting begins when the level
on the XTAL1 pin meets the V
IH2
criteria. At 33MHz, this time is 1.99ms.
Note 2:
EPROM PROGRAMMING AND VERIFICATION
(V
CC
= 4.5V to 5.5V, T
A
= +21 C to +27°C.)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Programming Voltage
Programming Supply Current
Oscillator Frequency
Address Setup to
PROG
Low
Address Hold after
PROG
Data Setup to
PROG
Low
Data Hold after
PROG
Enable High to V
PP
V
PP
Setup to
PROG
Low
V
PP
Hold after
PROG
PROG
Width
Address to Data Valid
Enable Low to Data Valid
Data Float after Enable
PROG
High to
PROG
Low
V
PP
I
PP
1/t
CLCL
t
AVGL
t
GHAX
t
DVGL
t
GHDX
t
EHSH
t
SHGL
t
SHGL
t
GLGH
t
AVQV
t
ELQV
t
EHQZ
t
GHGL
12.5
4
48t
CLCL
48 t
CLCL
48 t
CLCL
48 t
CLCL
48 t
CLCL
10
10
90
0
10
13.0
50
6
110
48 t
CLCL
48 t
CLCL
48 t
CLCL
V
mA
MHz
μs
μs
μs
μs
1
Note 1:
All voltages are referenced to ground.
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