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DS80C410/DS80C411 Network Microcontrollers with Ethernet and CAN
6 of 102
PARAMETER
SYMBOL
MIN
MAX
UNITS
STRETCH VALUES
C
ST
(MD2:0)
C
ST
= 0
1 C
ST
3
4 C
ST
7
C
ST
= 0
1 C
ST
3
4 C
ST
7
C
ST
= 0
1 C
ST
3
4 C
ST
7
C
ST
= 0
t
CLCL
- 5
2t
CLCL
- 5
6t
CLCL
- 5
2t
CLCL
+ t
CLCH
- 19
(4 x C
ST
+ 1) t
CLCL
- 19
(4 x C
ST
+ 5) t
CLCL
- 19
3t
CLCL
- 19
(4 x C
ST
+ 2)t
CLCL
- 19
(4 x C
ST
+ 10)t
CLCL
- 20
3t
CLCL
+ t
CLCH
- 22
(4 x C
ST
+ 2)t
CLCL
+ t
CLCH
-
22
(4 x C
ST
+ 10)t
CLCL
+ t
CLCH
-
22
t
CLCH
+ 6
t
CLCL
+ 6
5t
CLCL
+ 6
(Note 2)
6
t
CLCL
+ 6
5t
CLCL
+ 6
t
CHCL
+ 13
t
CLCL
+ t
CHCL
+ 13
5t
CLCL
+ t
CHCL
+ 13
Data Float After
RD
(P3.7 or
PSEN
) High
t
RHDZ
ns
ALE Low to Valid Data In
t
LLDV
ns
Port 0 Address to Valid Data
In
t
AVDV0
ns
1 C
ST
3
Port 2, 4, 6 Address, Port 4
CE, or Port 5 PCE to Valid
Data In
t
AVDV2
ns
4 C
ST
7
t
CLCH
- 3
t
CLCL
- 3
5t
CLCL
- 3
t
CLCL
– 6.5
2t
CLCL
– 6.5
10t
CLCL
– 7
t
CLCL
+ t
CLCH
- 7
2t
CLCL
+ t
CLCH
- 7
10t
CLCL
+ t
CLCH
- 7
0
t
CLCL
- 5
2
CLCL
- 8
6t
CLCL
- 8
C
ST
= 0
1 C
ST
3
4 C
ST
7
C
ST
= 0
1 C
ST
3
4 C
ST
7
C
ST
= 0
1 C
ST
3
4 C
ST
7
C
ST
= 0
1 C
ST
3
4 C
ST
7
0 C
ST
7
C
ST
= 0
1 C
ST
3
4 C
ST
7
C
ST
= 0
1 C
ST
3
4 C
ST
7
ALE Low to (
RD
or
PSEN
) or
WR
Low
t
LLWL
ns
Port 0 Address to (
RD
or
PSEN
) or
WR
Low
t
AVWL0
ns
Port 2, 4 Address, Port 4 CE,
Port 5 PCE, to (
RD
or
PSEN
)
or
WR
Low
Data Valid to
WR
Transition
t
AVWL2
ns
t
QVWX
ns
Data Hold After
WR
High
t
WHQX
ns
RD
Low to Address Float
t
RLAZ
-2.5
t
CLCL
– 2.5
5t
CLCL
– 2.5
t
CHCL
-5
t
CLCL
+ t
CHCL
- 5
5t
CLCL
+ t
CHCL
- 5
(
RD
or
PSEN
) or
WR
High to
ALE
t
WHLH
ns
(
RD
or
PSEN
) or
WR
High to
Port 4 CE or Port 5 PCE
High
t
WHLH2
ns
Note 1:
AC electrical characteristics assume 50% duty cycle for the oscillator, oscillator frequency
≤
75MHz, and are not 100% production
tested, but are guaranteed by design.
For a MOVX read operation, on the falling edge of ALE, Port 0 is held by a weak latch until overdriven by external memory.
All parameters apply to both commercial and industrial temperature operation, unless otherwise noted.
CST is the stretch cycle value as determined by the MD2, MD1, and MD0 bits of the CKCON register. t
CLCL
, t
CLCH
, t
CHCL
are time
periods associated with the internal system clock and are related to the external clock. See the
System Clock Time Periods
table.
All signals characterized with load capacitance of 80pF except Port 0, Port 2, ALE,
PSEN
,
RD,
and
WR
with 100pF. The following
signals, when configured for memory interface, are also characterized with 100pF loading: Port 4 (
CE0-3
, A16–A19), Port 5.4–5.7
(
PCE0-3
), Port 6.0–6.5 (
CE4-7
, A20, A21), Port 7 (demultiplexed mode A0–A7).
References to the XTAL, XTAL1 or CLK signal in the timing diagrams are to assist in determining the relative occurrence of events,
not for determining absolute signal timing with respect to the external clock.
Note 2:
Note 3:
Note 4:
Note 5:
Note 6: