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參數(shù)資料
| 型號： | DS80C411-FNY |
| 英文描述： | Network Microcontrollers with Ethernet and CAN |
| 中文描述： | 網(wǎng)絡(luò)微控制器與以太網(wǎng)和CAN |
| 文件頁數(shù)： | 3/102頁 |
| 文件大?。?/td> | 2637K |
| 代理商： | DS80C411-FNY |
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DS80C410/DS80C411 Network Microcontrollers with Ethernet and CAN
Note 1:
Note 2:
3 of 102
Specifications to -40°C are guaranteed by design and not production tested.
The user should note that this part is tested and guaranteed to operate down to V
CC3
= 3.0V and V
CC1
= 1.62V, while the reset
thresholds for those supplies, V
and V
respectively, may be above or below those points. When the reset threshold for a
given supply is greater than the guaranteed minimum operating voltage, that reset threshold should be considered the minimum
operating point since execution ceases once the part enters the reset state. When the reset threshold for a given supply is lower
than the guaranteed minimum operating voltage, there exists a range of voltages for either supply, (V
< V
< 1.62V) or (V
< V
CC1
< 3.0V), where the processor’s operation is not guaranteed, and the reset trip point has not been reached. This should not
be an issue in most applications, but should be considered when proper operation must be maintained at all times. For these
applications, it may be desirable to use a more accurate external reset.
While the specifications for V
PFW3
and V
RST3
overlap, the design of the hardware makes it such that this is not possible. Within the
ranges given, there is a guaranteed separation between these two voltages.
Note 3:
Note 4:
Current measured with 75MHz clock source on XTAL1, V
CC3
= 3.6V, V
CC1
= 2.0V,
EA
and RST = 0V, Port0 = V
CC3
, all other pins
disconnected.
While the specifications for V
PFW1
and V
RST1
overlap, the design of the hardware makes it such that this is not possible. Within the
ranges given, there will be a guaranteed separation between these two voltages.
Certain pins exhibit stronger drive capability when being used to address external memory. These pins and associated memory
interface function (in parentheses) are as follows: Port 3.6-3.7 (
WR
,
RD
), Port 4 (
CE0-3
, A16-A19), Port 5.4-5.7 (
PCE0-3
), Port 6.0-
6.5 (
CE4-7
, A20, A21), Port 7 (demultiplexed mode A0-A7).
This measurement reflects the weak I/O pullup state that persists following the momentary strong 0 to 1 port pin drive (V
OH2
). This
I/O pin state can be achieved by applying RST = V
CC3.
The measurement reflects the momentary strong port pin drive during a 0-to-1 transition in I/O mode. During this period, a one shot
circuit drives the ports hard for two clock cycles. A weak pullup device (V
OH1
) remains in effect following the strong two-clock cycle
drive. If a port 4 or 6 pin is functioning in memory mode with pin state of 0 and the SFR bit contains a 1, changing the pin to an I/O
mode (by writing to P4CNT, for example) does not enable the two-cycle strong pullup.
Port 3 pins 3.6 (
WR
) and 3.7(
RD
) have a stronger than normal pullup drive for only one system clock period following the transition
of either
WR
or
RD
from a 0 to a 1.
This is the current required from an external circuit to hold a logic low level on an I/O pin while the corresponding port latch bit is set
to 1. This is only the current required to
hold
the low level; transitions from 1 to 0 on an I/O pin also have to overcome the transition
current.
Following the 0 to 1 one-shot timeout, ports in I/O mode source transition current when being pulled down externally. It reaches a
maximum at approximately 2V.
During external addressing mode, weak latches are used to maintain the previously driven state on the pin until such time that the
Port 0 pin is driven by an external memory source.
The OW pin (when configured to output a 1) at V
IN
= 5.5V,
EA
,
MUX
, and all MII inputs (TXCLk, RXCLk, RX_DV, RX_ER, RXD[3:0],
CRS, COL, MDIO) at V
IN
= 3.6V.
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| DS80C411-FNY+ | 功能描述:8位微控制器 -MCU Network MCU w/Ethernet & CAN RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| DS80CH11 | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:System Energy Manager |
| DS80CH11+E02 | 制造商:Maxim from Components Direct 功能描述:MAXIM DS80CH11+E02 SYSTEM ENERGY MANAGERS - Trays 制造商:Maxim 功能描述:Maxim DS80CH11+E02 System Energy Managers |
| DS80CH11-E02 | 制造商:Maxim from Components Direct 功能描述:MAXIM DS80CH11-E02 SYSTEM ENERGY MANAGERS - Trays 制造商:Maxim 功能描述:Maxim DS80CH11-E02 System Energy Managers |
| DS80E100 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:5 to 12.5 Gbps, Power-Saver Equalizer for Backplanes and Cables |
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