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參數(shù)資料
| 型號： | DS80C323-QND/T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 16/38頁 |
| 文件大小： | 0K |
| 描述： | IC MCU HI SPEED 18MHZ IND 44PLCC |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 500 |
| 系列： | 80C |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 18MHz |
| 連通性： | EBI/EMI，SIO，UART/USART |
| 外圍設(shè)備： | 電源故障復(fù)位，WDT |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲器類型： | ROMless |
| RAM 容量： | 256 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.5 V ~ 5.5 V |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 包裝： | 帶卷 (TR) |
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DS80C320/DS80C323 High-Speed/Low-Power Microcontrollers
23 of 38
AC CHARACTERISTICS—DS80C320
33MHz
VARIABLE CLOCK
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
UNITS
External
Oscillator
0
33
0
33
Oscillator
Frequency
External
Crystal
1/tCLCL
1
33
1
33
MHz
ALE Pulse Width
tLHLL
34
1.5tCLCL-11
ns
Port 0 Address Valid to
ALE Low
tAVLL
4
0.5tCLCL-11
ns
Address Hold After
ALE Low
tLLAX1
2
(Note 5)
0.25tCLCL-5
(Note 5)
ns
Address Hold After
ALE Low for MOVX WR
tLLAX2
6
0.5tCLCL-9
ns
ALE Low to Valid
Instruction In
tLLIV
49
2.5tCLCL-27
ns
ALE Low to PSEN Low
tLLPL
0.5
0.25tCLCL-7
ns
PSEN
Pulse Width
tPLPH
61
2.25tCLCL-7
ns
PSEN
Low to Valid
Instruction In
tPLIV
48
2.25tCLCL-21
ns
Input Instruction Hold
After PSEN
tPXIX
0
ns
Input Instruction Float
After PSEN
tPXIZ
25
tCLCL-5
ns
Port 0 Address to Valid
Instruction In
tAVIV1
64
3tCLCL-27
ns
Port 2 Address to Valid
Instruction In
tAVIV2
73
3.5tCLCL-33
ns
PSEN
Low to Address Float
tPLAZ
(Note 5)
ns
NOTES FOR DS80C320 AC ELECTRICAL CHARACTERISTICS
All parameters apply to both commercial and industrial temperature operation unless otherwise noted. Specifications to -40°C
are guaranteed by design and are not production tested. AC electrical characteristics assume 50% duty cycle for the oscillator,
oscillator frequency > 16MHz, and are not 100% tested, but are guaranteed by design.
1. All signals rated over operating temperature at 33MHz.
2. All signals characterized with load capacitance of 80pF except Port 0, ALE, PSEN , RD and WR at 100pF.
Note that loading should be approximately equal for valid timing.
3. Interfacing to memory devices with float times (turn off times) over 30ns may cause contention. This will not
damage the parts but will cause an increase in operating current.
4. Specifications assume a 50% duty cycle for the oscillator. Port 2 timing will change with the duty cycle
variations.
5. Address is held in a weak latch until over driven by external memory.
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相關(guān)代理商/技術(shù)參數(shù) |
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| DS80C323-QNG | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:High-Speed Microcontroller User Guide |
| DS80C323-QNL | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:High-Speed Microcontroller User Guide |
| DS80C323-QNR | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:High-Speed Microcontroller User Guide |
| DS80C323-WCD | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:High-Speed Microcontroller User Guide |
| DS80C323-WCG | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:High-Speed Microcontroller User Guide |
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