參數(shù)資料
型號: DS75LXS+
廠商: Maxim Integrated
文件頁數(shù): 3/13頁
文件大?。?/td> 228K
描述: IC THERMOMETER/STAT DIG 8-SOIC
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 100
功能: 溫度計,恒溫計
傳感器類型: 內部
感應溫度: -55°C ~ 125°C
精確度: ±3°C(最小值)
拓撲: ADC(三角積分型),比較器,寄存器庫
輸出類型: I²C?/SMBus?
輸出警報:
輸出風扇:
電源電壓: 2.7 V ~ 5.5 V
工作溫度: -55°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應商設備封裝: 8-SOIC
包裝: 管件
產(chǎn)品目錄頁面: 1435 (CN2011-ZH PDF)
DS75LX: Digital Thermometer and Thermostat with Extended Addressing
 
3 of 13   
 
 
 
 
SCL Frequency
f
SCL
 
 
 
400
kHz
AC ELECTRICAL CHARACTERISTICS (continued)
(1.7V d V
DD
 d 3.7V, T
A
 = -55癈 to +125癈.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX     UNITS
Bus Free Time Between
a STOP and START
Condition
t
BUF
(Note 7)
1.3
 
 
 
START and Repeated
START Hold Time from
Falling SCL
t
HD:STA
(Notes 7, 8)
600
 
 
 
ns
Low Period of SCL
t
LOW
(Note 7)
1.3
 
 
High Period of SCL
t
HIGH
(Note 7)
0.6
 
 
Repeated START
Condition Setup Time to
Rising SCL
t
SU:STA
(Note 7)
600
 
 
ns
Data-Out Hold Time from
Falling SCL
t
HD:DAT
(Notes 7, 9)
0
 
0.9
Data-In Setup Time to
Rising SCL
t
SU:DAT
(Note 7)
100
 
 
 
ns
Rise Time of SDA and
SCL (Receive)
t
R
(Notes 7, 10)
20 +
0.1C
B
B
 
300
ns
Fall Time of SDA and
SCL (Receive)
t
F
(Notes 7, 10)
20 +
 
0.1C
B
B
 
300
ns
Spike Suppression
Filter Time (Deglitch
Filter)
t
SS
 
0
 
50
ns
STOP Setup Time to
Rising SCL
t
SU:STO
(Note 7)
600
 
 
ns
Capacitive Load for Each
Bus Line
C
B
B
 
 
 
400
pF
Input Capacitance
C
I
 
 
5
 
pF
Serial Interface Reset
Time
t
TIMEOUT
SDA time low
(Notes 11, 12)
75
 
325
ms
 
Note 1:
V
DD
 must be decoupled with a high-quality 0.1礔 bypass capacitor. X5R or X7R ceramic surface-mount capacitors are
recommended.
Note 2:
Internal heating caused by O.S. loading causes the DS75LX to read approximately 0.5癈 higher if O.S. is sinking the max
rated current.
Note 3:
All voltages are referenced to ground.
Note 4:
I
DD
 specified with O.S. pin open and A0A2 pins grounded.
Note 5:
I
DD
 and address leakage specified with V
DD
 at 3.0V and SDA, SCL = 3.0V at 0癈 to +70癈.
Note 6:
Address pins A0, A1, A2 are directly connected to V
DD
, V
SS
, or floating with less than 50pF capacitive load.
Note 7:
See the timing diagram (Figure 1). All timing is referenced to 0.9 x V
DD
 and 0.1 x V
DD
.
Note 8:
After this period, the first clock pulse is generated.
Note 9:
The DS75LX provides an internal hold time of at least 75ns on the SDA signal to bridge the undefined region of SCL's falling
edge.
Note 10:     For example, if C
B
= 300pF, then t
R
[min] = t
F
[min] = 50ns.
Note 11:     This timeout applies only when the DS75LX is holding SDA low. Other devices can hold SDA low indefinitely and the DS75LX 
will not reset.
Note 12:     The DS75LX is available with timeout feature disabled upon special order. Contact Factory. 
 
PIN DESCRIPTION
PIN 
NAME 
FUNCTION
1
SDA
Data Input/Output for 2-Wire Serial Communication Port (Open Drain)
2
SCL
Clock Input for 2-Wire Serial Communication Port
3
O.S.
Thermostat Output Open Drain
4
GND
Ground
5
A
2
Address Input
6
A
1
Address Input
7
A
0
Address Input
8
V
DD
Supply Voltage. +1.7V to +3.7V supply pin. V
DD
  must have an external bypass
capacitor to GND. 0.1礔 X5R or X7R ceramic SMT caps recommended.
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