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參數(shù)資料
| 型號： | DS5001FP-16N |
| 元件分類： | 微處理器 |
| 英文描述： | 128k Soft Microprocessor Chip |
| 中文描述： | 128K的軟微處理器芯片 |
| 文件頁數(shù)： | 5/26頁 |
| 文件大?。?/td> | 557K |
| 代理商： | DS5001FP-16N |
DS5001FP
5 of 26
33, 35,
37
71, 69,
67, 65,
61, 59,
57, 55
9
and A15 respectively.
28, 26,
24, 23,
21, 20,
19, 18
BD7–0
Byte-Wide Data-Bus Bits 7–0
. This 8-bit, bidirectional bus is combined with the
nonmultiplexed address bus (BA14–0) to access NV SRAM. Decoding is performed on
CE1
and
CE2
. Read/write access is controlled by R/
W
. BD7–0 connect directly to an
SRAM, and optionally to a real-time clock or other peripheral.
Read/Write.
This signal provides the write enable to the SRAMs on the byte-wide bus. It
is controlled by the memory map and partition. The blocks selected as program (ROM) are
write-protected.
Chip Enable 1.
This is the primary decoded chip enable for memory access on the byte-
wide bus. It connects to the chip enable input of one SRAM.
CE1
is lithium-backed. It
remains in a logic high inactive state when V
CC
falls below V
LI
.
Non-battery-backed version of chip enable 1. This can be used with a 32kB EPROM. It
should not be used with a battery-backed chip.
Chip Enable 2.
This chip enable is provided to access a second 32k block of memory. It
connects to the chip enable input of one SRAM. When MSEL = 0, the micro converts
CE2
into A16 for a 128k x 8 SRAM.
CE2
is lithium-backed and remains at a logic high when
V
CC
falls below V
LI
.
Chip Enable 3.
This chip enable is provided to access a third 32k block of memory. It
connects to the chip enable input of one SRAM. When MSEL = 0, the micro converts
CE3
into A15 for a 128k x 8 SRAM.
CE3
is lithium-backed and remains at a logic high when
V
CC
falls below V
LI
.
Chip Enable 4.
This chip enable is provided to access a fourth 32k block of memory. It
connects to the chip-enable input of one SRAM. When MSEL = 0, this signal is unused.
CE4
is lithium-backed and remains at a logic high when V
CC
< V
LI
.
Peripheral Enable 1.
Accesses data memory between addresses 0000h and 3FFFh when
the PES bit is set to a logic 1. Commonly used to chip enable a byte-wide real-time clock
such as the DS1283.
PE1
is lithium-backed and remains at a logic high when V
CC
falls
below V
LI
. Connect
PE1
to battery-backed functions only.
Peripheral Enable 2.
Accesses data memory between addresses 4000h and 7FFFh when
the PES bit is set to a logic 1.
PE2
is lithium-backed and remains at a logic high when V
CC
falls below V
LI
. Connect
PE2
to battery-backed functions only.
Peripheral Enable 3.
Accesses data memory between addresses 8000h and BFFFh when
the PES bit is set to a logic 1.
PE3
is not lithium-backed and can be connected to any type
of peripheral function. If connected to a battery-backed chip, it needs additional circuitry to
maintain the chip enable in an inactive state when V
CC
< V
LI
.
Peripheral Enable 4.
Accesses data memory between addresses C000h and FFFFh when
the PES bit is set to a logic 1.
PE4
is not lithium-backed and can be connected to any type
of peripheral function. If connected to a battery-backed chip, it needs additional circuitry to
maintain the chip enable in an inactive state when V
CC
< V
LI
.
Invokes the bootstrap loader on a falling edge.
This signal should be debounced so that
only one edge is detected. If connected to ground, the micro enters bootstrap loading on
power-up. This signal is pulled up internally.
This I/O pin (open drain with internal pullup) indicates that the power supply (V
CC
)
has fallen below the V
CCmin
level and the micro is in a reset state.
When this occurs, the
DS5001FP drives this pin to a logic 0. Because the micro is lithium-backed, this signal is
guaranteed even when V
CC
= 0V. Because it is an I/O pin, it also forces a reset if pulled
low externally. This allows multiple parts to synchronize their power-down resets.
This output goes to a logic 0 to indicate that V
CC
< V
LI
and the micro has switched to
lithium backup. Because the micro is lithium-backed, this signal is guaranteed even when
V
CC
= 0V. The normal application of this signal is to control lithium powered current to
isolate battery-backed functions from non-battery-backed functions.
Memory Select.
This signal controls the memory size selection. When MSEL = +5V, the
DS5001FP expects to use 32k x 8 SRAMs. When MSEL = 0V, the DS5001FP expects to
use a 128k x 8 SRAM. MSEL must be connected regardless of partition, mode, etc.
No Connect.
10
37
R/
W
74
29
CE1
72
N/A
CE1N
2
33
CE2
63
22
CE3
62
N/A
CE4
78
N/A
PE1
3
N/A
PE2
22
N/A
PE3
23
N/A
PE4
32
N/A
PROG
42
N/A
VRST
43
N/A
PF
14
40
MSEL
73
NC
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS5001FP-16N+ | 功能描述:微處理器 - MPU Soft MCU Chip RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| DS5001FPN08 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| DS5001FPN12 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| DS5001FPN16 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| DS5002FMN+16 | 制造商:Maxim Integrated Products 功能描述:SECUR MICR DBL METAL 16MHZ IND PB-F - Rail/Tube |
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