參數(shù)資料
型號: DS5001FP-16N
元件分類: 微處理器
英文描述: 128k Soft Microprocessor Chip
中文描述: 128K的軟微處理器芯片
文件頁數(shù): 13/26頁
文件大小: 557K
代理商: DS5001FP-16N
DS5001FP
13 of 26
AC CHARACTERISTICS
EXPANDED BUS MODE TIMING SPECIFICATIONS
(T
A
= 0°C to +70°C; V
CC
= 5V ±10%)
#
PARAMETER
1
Oscillator Frequency
2
ALE Pulse Width
3
Address Valid to ALE Low
4
Address Hold After ALE Low
ALE Low to Valid Instruction In
at 12MHz
at 16MHz
6
ALE Low to
PSEN
Low
7
PSEN
Pulse Width
PSEN
Low to Valid Instruction In
at 12MHz
at 16MHz
Input Instruction Hold After
PSEN
Going
High
Input Instruction Float After
PSEN
Going
High
11
Address Hold After
PSEN
Going High
Address Valid to Valid Instruction In
at 12MHz
at 16MHz
13
PSEN
Low to Address Float
14
RD
Pulse Width
15
WR
Pulse Width
RD
Low to Valid Data In
at 12MHz
at 16MHz
17
Data Hold After
RD
High
18
Data Float After
RD
High
ALE Low to Valid Data In at 12MHz
at 16MHz
Valid Address to Valid Data In at 12MHz
at 16MHz
21
ALE Low to
RD
or
WR
Low
22
Address Valid to
RD
or
WR
Low
23
Data Valid to
WR
Going Low
Data Valid to
WR
High
at 12MHz
at 16MHz
25
Data Valid After
WR
High
26
RD
Low to Address Float
27
RD
or
WR
High to ALE High
SYMBOL
1/ t
CLK
t
ALPW
t
AVALL
t
AVAAV
MIN
1.0
2t
CLK
- 40
t
CLK
- 40
t
CLK
- 35
MAX
16
UNITS
MHz
ns
ns
ns
5
t
ALLVI
4t
CLK
- 150
4t
CLK
- 90
ns
ns
t
ALLPSL
t
PSPW
t
CLK
- 25
3t
CLK
- 35
ns
ns
8
t
PSLVI
3t
CLK
- 150
3t
CLK
- 90
ns
ns
9
t
PSIV
0
ns
10
t
PSIX
t
CLK
- 20
ns
t
PSAV
t
CLK
- 8
ns
12
t
AVVI
5t
CLK
- 150
5t
CLK
- 90
ns
ns
t
PSLAZ
t
RDPW
t
WRPW
0
ns
ns
ns
ns
ns
ns
ns
6t
CLK
- 100
6t
CLK
- 100
16
t
RDLDV
5t
CLK
- 165
5t
CLK
- 105
t
RDHDV
t
RDHDZ
0
2t
CLK
- 70
8t
CLK
- 150
8t
CLK
- 90
9t
CLK
- 165
9t
CLK
- 105
3t
CLK
+ 50
19
t
ALLVD
ns
20
t
AVDV
ns
t
ALLRDL
t
AVRDL
t
DVWRL
3t
CLK
- 50
4t
CLK
- 130
t
CLK
- 60
7t
CLK
- 150
7t
CLK
- 90
t
CLK
- 50
ns
ns
ns
24
t
DVWRH
ns
t
WRHDV
t
RDLAZ
t
RDHALH
ns
ns
ns
0
t
CLK
- 40
t
CLK
+ 50
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