參數(shù)資料
型號(hào): DS5000T-8-8
英文描述: Soft Microcontroller
中文描述: 軟微控制器
文件頁(yè)數(shù): 10/19頁(yè)
文件大小: 131K
代理商: DS5000T-8-8
DS5000(T)
021998 10/19
AC CHARACTERISTICS
EXPANDED BUS MODE TIMING SPECIFICATIONS
(t
A
= 0
°
C to70
°
C; V
CC
= 5V + 5%)
MIN
MAX
#
PARAMETER
SYMBOL
UNITS
1
Oscillator Frequency
1/t
CLK
t
ALPW
t
AVALL
t
AVAAV
t
ALLVI
1.0
16
MHz
2
ALE Pulse Width
2t
CLK
–40
t
CLK
–40
t
CLK
–35
ns
3
Address Valid to ALE Low
ns
4
Address Hold After ALE Low
ns
5
ALE Low to Valid Instr. In
@12 MHz
@16 MHz
4t
CLK
–150
4t
CLK
–90
ns
ns
6
ALE Low to PSEN Low
t
ALLPSL
t
PSPW
t
PSLVI
t
CLK
–25
3t
CLK
–35
ns
7
PSEN Pulse Width
ns
8
PSEN Low to Valid Instr. In
@12 MHz
@16 MHz
3t
CLK
–150
3t
CLK
–90
ns
ns
9
Input Instr. Hold after PSEN Going High
t
PSIV
t
PSIX
t
PSAV
t
AVVI
0
ns
10
Input Instr. Float after PSEN Going High
t
CLK
–20
ns
11
Address Hold after PSEN Going High
t
CLK
–8
ns
12
Address Valid to Valid Instr. In @12 MHz
@16 MHz
5t
CLK
–150
5t
CLK
–90
ns
ns
13
PSEN Low to Address Float
t
PSLAZ
t
RDPW
t
WRPW
t
RDLDV
0
ns
14
RD Pulse Width
6t
CLK
–100
6t
CLK
–100
ns
15
WR Pulse Width
ns
16
RD Low to Valid Data In
@12 MHz
@16 MHz
5t
CLK
–165
5t
CLK
–105
ns
ns
17
Data Hold after RD High
t
RDHDV
t
RDHDZ
t
ALLVD
0
ns
18
Data Float after RD High
2t
CLK
–70
8
CLK
–150
8t
CLK
–90
9t
CLK
–165
9t
CLK
–105
3t
CLK
+50
ns
19
ALE Low to Valid Data In
@12 MHz
@16 MHz
ns
ns
20
Valid Addr. to Valid Data In
@12 MHz
@16 MHz
t
AVDV
ns
ns
21
ALE Low to RD or WR Low
t
ALLRDL
t
AVRDL
t
DVWRL
t
DVWRH
3t
CLK
–50
4t
CLK
–130
t
CLK
–60
7t
CLK
–150
7t
CLK
–90
ns
22
Address Valid to RD or WR Low
ns
23
Data Valid to WR Going Low
ns
24
Data Valid to WR High
@12 MHz
@16 MHz
ns
ns
25
Data Valid after WR High
t
WRHDV
t
RDLAZ
t
RDHALH
t
CLK
–50
ns
26
RD Low to Address Float
0
ns
27
RD or WR High to ALE High
t
CLK
–40
t
CLK
+50
ns
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