參數(shù)資料
型號: DS4M133D+33
廠商: Maxim Integrated Products
文件頁數(shù): 1/7頁
文件大?。?/td> 0K
描述: IC OSC CLOCK 133.33MHZ 10-LCCC
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 34
類型: 時鐘振蕩器
頻率: 133.33MHz
電源電壓: 3.135 V ~ 3.465 V
電流 - 電源: 74mA
工作溫度: -40°C ~ 85°C
封裝/外殼: 10-LCCC 裸露焊盤
包裝: 管件
供應(yīng)商設(shè)備封裝: 10-LCCC
安裝類型: 表面貼裝
產(chǎn)品目錄頁面: 1433 (CN2011-ZH PDF)
General Description
The DS4M125/DS4M133/DS4M200 are margining clock
oscillators with LVPECL or LVDS outputs. They are
designed to fit in a 5mm x 3.2mm ceramic package with
an AT-cut fundamental-mode crystal to form a complete
clock oscillator. The circuit can generate the following
frequencies and their ±5% frequency deviations:
125MHz, 133.33MHz, and 200MHz. The DS4M125/
DS4M133/DS4M200 employ a low-jitter PLL to generate
the frequencies. The typical phase jitter is less than
0.9ps RMS from 12kHz to 20MHz.
Frequency margining is a circuit operation to change
the output frequency to 5% higher or 5% lower than the
nominal frequency. Frequency margining is accom-
plished through the margining select pin, MS. This
three-state input pin accepts a three-level voltage signal
to control the output frequency. In a low-level state, the
output frequency is set to the nominal frequency. When
set to a high-level state, the frequency output is set to
the nominal frequency plus 5%. When set to the mid-
level state, the frequency output is equal to the nominal
frequency minus 5%. If left open, the MS pin is pulled
low by an internal 100k
Ω (nominal) pulldown resistor.
The DS4M125/DS4M133/DS4M200 are available with
either an LVPECL or LVDS output. The output can be
disabled by pulling the OE pin low. When disabled,
both OUTP and OUTN levels of the LVPECL driver go to
the LVPECL bias voltage, while the output of the LVDS
driver is a logical one. The OE input is an active-high
logic signal and has an internal 100k
Ω pullup resistor.
When OE is in a logic-high state, the OUTP and OUTN
outputs are enabled.
The devices operate from a single 3.3V supply voltage.
Applications
Memory Clocks
RAID Systems
Features
Frequency Margining: ±5%
Nominal Clock Output Frequencies: 125MHz,
133.33MHz, and 200MHz
Jitter < 0.9ps RMS from 12kHz to 20MHz
LVPECL or LVDS Output
3.3V Operating Voltage
Operating Temperature Range: -40°C to +85°C
Supply Current: < 100mA at 3.3V
Excellent Power-Supply Noise Rejection
5mm x 3.2mm Ceramic LCCC Package
Output Enable/Disable
DS4M125/DS4M133/DS4M200
3.3V Margining Clock Oscillator with
LVPECL/LVDS Output
________________________________________________________________
Maxim Integrated Products
1
Ordering Information
DS4M125/
DS4M133/
DS4M200
DS4M125/
DS4M133/
DS4M200
VCC
OUTP
OUTN
LVDS OPTION
OE
MS
GND
0.01
μF
0.1
μF
100
Ω
OE
MS
GND
VCC
OUTP
OUTN
LVPECL OPTION
0.01
μF
0.1
μF
50
Ω
50
Ω
PECL_BIAS AT
VCC - 2.0V
Typical Operating Circuit
Rev 0; 12/07
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
PART
TEMP RANGE
PIN-PACKAGE
DS4M125P+33
-40
°C to +85°C
10 LCCC
DS4M125D+33
-40
°C to +85°C
10 LCCC
DS4M133P+33
-40
°C to +85°C
10 LCCC
DS4M133D+33
-40
°C to +85°C
10 LCCC
DS4M200P+33
-40
°C to +85°C
10 LCCC
DS4M200D+33
-40
°C to +85°C
10 LCCC
+
Denotes a lead(Pb)-free package. The lead finish is JESD97
category e4 (Au over Ni) and is compatible with both lead-based
and lead-free soldering processes.
Pin Configuration and Selector Guide appear at end of
data sheet.
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DS4M133P+33 功能描述:標(biāo)準(zhǔn)時鐘振蕩器 3.3V Margining Clock w/LVPECL/LVDS Output RoHS:否 制造商:AVX 產(chǎn)品:Standard Clock Oscillators 封裝 / 箱體:7 mm x 5 mm 頻率:75 MHz 頻率穩(wěn)定性:50 PPM 電源電壓:2.5 V 負(fù)載電容: 端接類型:SMD/SMT 最小工作溫度:0 C 最大工作溫度:+ 70 C 輸出格式:LVDS 尺寸: 封裝:Reel 系列:
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